Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
01/2013
01/31/2013WO2013013843A1 Method for assembling microelectronic-chip device in fabric, chip device, and fabric containing a crimped chip device
01/31/2013WO2012152272A3 Optical recording device
01/31/2013US20130027113 Power Semiconductor Chip Having Two Metal Layers on One Face
01/31/2013US20130027066 Transistor test structure
01/31/2013US20130026718 Die seal ring structure
01/31/2013US20130026662 Epoxy resin composition for semiconductor encapsulation and semiconductor device using the same
01/31/2013US20130026661 Liquid epoxy resin composition for semiconductor encapsulation, and semiconductor device using the same
01/31/2013US20130026660 Liquid epoxy resin composition for semiconductor encapsulation, and semiconductor device using the same
01/31/2013US20130026659 Microelectronic component
01/31/2013US20130026658 Wafer level chip scale package for wire-bonding connection
01/31/2013US20130026657 Semiconductor package and method of fabricating the same
01/31/2013US20130026656 Semiconductor packages and electronic systems including the same
01/31/2013US20130026655 Chip package structure and method of manufacturing the same
01/31/2013US20130026654 Semiconductor Device and Method of Forming Vertical Interconnect in FO-WLCSP Using Leadframe Disposed Between Semiconductor Die
01/31/2013US20130026653 Method for manufacturing semiconductor device
01/31/2013US20130026652 Semiconductor device
01/31/2013US20130026651 Semiconductor package and stacked semiconductor package having the same
01/31/2013US20130026650 Semiconductor device, semiconductor module structure configured by vertically stacking semiconductor devices, and manufacturing method thereof
01/31/2013US20130026649 Semiconductor device and manufacturing method therefor
01/31/2013US20130026648 Film for forming semiconductor protection film, and semiconductor device
01/31/2013US20130026647 Via structure
01/31/2013US20130026646 Passivated through wafer vias in low-doped semiconductor substrates
01/31/2013US20130026645 Low stress vias
01/31/2013US20130026644 Photoactive Compound Gradient Photoresist
01/31/2013US20130026643 Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
01/31/2013US20130026642 Integrated circuit package including a direct connect pad, a blind via, and a bond pad electrically coupled to the direct connect pad
01/31/2013US20130026641 Conductor contact structure and forming method, and photomask pattern generating method for defining such conductor contact structure
01/31/2013US20130026640 Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
01/31/2013US20130026639 Method of fabricating dual damascene structures using a multilevel multiple exposure patterning scheme
01/31/2013US20130026638 Wafer-Level Chip Scale Package
01/31/2013US20130026637 Metal gate electrode of a field effect transistor
01/31/2013US20130026636 Laminated and sintered ceramic circuit board, and semiconductor package including the circuit board
01/31/2013US20130026635 Hybrid Copper Interconnect Structure and Method of Fabricating Same
01/31/2013US20130026634 Hybrid Interconnect Technology
01/31/2013US20130026633 Multilayer Metallization with Stress-Reducing Interlayer
01/31/2013US20130026632 Semiconductor element-embedded wiring substrate
01/31/2013US20130026631 Semiconductor apparatus and manufacturing method thereof
01/31/2013US20130026630 Flip chips having multiple solder bump geometries
01/31/2013US20130026629 Semiconductor device, semiconductor device unit, and semiconductor device production method
01/31/2013US20130026628 Flip Chip Interconnection having Narrow Interconnection Sites on the Substrate
01/31/2013US20130026627 Electronic chip comprising connection pillars and manufacturing method
01/31/2013US20130026626 Method for forming bumps and substrate including the bumps
01/31/2013US20130026625 Flip-chip semiconductor device having anisotropic electrical interconnection and substrate utilized for the package
01/31/2013US20130026624 Coaxial solder bump support structure
01/31/2013US20130026623 Semiconductor Devices, Packaging Methods and Structures
01/31/2013US20130026622 Bump structures in semiconductor device and packaging assembly
01/31/2013US20130026621 Metal bump structure
01/31/2013US20130026620 Self-aligning conductive bump structure and method of making the same
01/31/2013US20130026619 Bump structures
01/31/2013US20130026618 Method and device for circuit routing by way of under-bump metallization
01/31/2013US20130026617 Methods of forming a metal silicide region in an integrated circuit
01/31/2013US20130026616 Power device package module and manufacturing method thereof
01/31/2013US20130026615 Double-side exposed semiconductor device and its manufacturing method
01/31/2013US20130026614 Structure and method for bump to landing trace ratio
01/31/2013US20130026613 Semiconductor device
01/31/2013US20130026612 Method of shielding through silicon vias in a passive interposer
01/31/2013US20130026609 Package assembly including a semiconductor substrate with stress relief structure
01/31/2013US20130026606 Tsv pillar as an interconnecting structure
01/31/2013US20130026605 WLCSP for Small, High Volume Die
01/31/2013US20130026601 Semiconductor Device and Method for Manufacturing a Semiconductor
01/31/2013US20130026599 Semiconductor device
01/31/2013US20130026570 Borderless contact for ultra-thin body devices
01/31/2013US20130026550 Semiconductor integrated circuit
01/31/2013US20130026492 Diamond Semiconductor System and Method
01/31/2013US20130026490 Glass/ceramics replacement of epoxy for high temperature hermetically sealed non-axial electronic packages
01/31/2013US20130026466 Testing architecture of circuits integrated on a wafer
01/31/2013US20130026464 Test pattern for measuring semiconductor alloys using x-ray diffraction
01/31/2013US20130026463 Electronic device and manufacturing method for same
01/31/2013US20130026308 Mounting bracket means for solar arrays and the like
01/31/2013US20130025931 Electronic Component and Method for Manufacturing the Same
01/31/2013DE112010001158B4 Heisswasserkühlvorrichtung Hot water cooler
01/31/2013DE112006004098B4 Halbleiter-Baugruppe mit einer Lead-Frame-Anordnung mit mindestens zwei Halbleiterchips und Verfahren zu deren Herstellung Semiconductor package with a lead frame assembly having at least two semiconductor chips and processes for their preparation
01/31/2013DE10231168B4 Verfahren zur Herstellung von federelastischen elektrischen Kontakten Process for the preparation of resilient electrical contacts
01/31/2013DE102012212890A1 High-Side Schalter High-side switch
01/31/2013DE102012212515A1 Semiconductor device for switching of high current, has guard ring that is located on semiconductor substrate so as to surround semiconductor element, and channel stopper which is extended along inside wall of recess
01/31/2013DE102012211213A1 Eine Halbleitervorrichtung, die einen vertikalkavitätsoberflächenemittierenden Laser (VCSEL) und eine darin integrierte Schutzdiode aufweist und reduzierte Kapazität aufweist, um es dem VCSEL zu ermöglichen, hoheBetriebsgeschwindigkeiten zu erreichen A semiconductor device having a vertikalkavitätsoberflächenemittierenden laser (VCSEL), and an integrated protection diode therein and having reduced capacity, to allow the VCSEL to achieve high operating speeds
01/31/2013DE102012207311A1 Siliziumcarbid-Halbleitervorrichtung Silicon carbide semiconductor device
01/31/2013DE102012106662A1 Mehrschichtenmetallisierung mit beanspruchungsreduzierender Zwischenschicht Mehrschichtenmetallisierung with load-reducing intermediate layer
01/31/2013DE102012106566A1 Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche Power semiconductor chip with two metal layers on a surface
01/31/2013DE102012106473A1 Struktur und Verfahren für das Kontakthügel-Anlagespur-Verhältnis Structure and procedures for the bump-track system for money
01/31/2013DE102012106266A1 Stromversorgungsgehäusemodul und Verfahren zur Herstellung eines Stromversorgungsgehäusemoduls Power supply module and housing method for manufacturing a power supply module housing
01/31/2013DE102012103784A1 Chipgehäusemodul für einen Chip und Verfahren zum Bilden eines Chipgehäusemoduls Chip module housing for a chip and method of forming a chip package module
01/31/2013DE102012103519B3 Kühlkörper und Verfahren zum Herstellen des gleichen Heat sink and method for manufacturing the same
01/31/2013DE102011109006A1 Gehäuse für einen Halbleiterchip und Halbleiterchip mit einem Gehäuse A housing for a semiconductor chip and the semiconductor chip with a housing
01/31/2013DE102011080153A1 Power semiconductor module for use at outer wall of motor, has component or contact surface exhibiting direct connection with one substrate and arranged between respective substrates and metallization layer that is attached on substrates
01/31/2013DE102011079708A1 Trägervorrichtung, elektrische vorrichtung mit einer trägervorrichtung und verfahren zur herstellung dieser Support means, electrical assembly having a support apparatus and process for producing these
01/31/2013DE102004031687B4 Leistungsverstärkeranordnung Power amplifier arrangement
01/31/2013CA2843371A1 Heat dissipating component for semiconductor element
01/30/2013EP2552020A2 Electronic device, oscillator, and method of manufacturing electronic device
01/30/2013EP2551901A1 Semiconductor device and method for manufacturing a semiconductor
01/30/2013EP2551324A1 Use of an anisotropic fluoropolymer for the conduction of heat
01/30/2013EP2550676A1 Ic package stiffener with beam
01/30/2013EP2550674A1 Three dimensional inductor and transformer design methodology of glass technology
01/30/2013CN202713119U 变频器 Drive
01/30/2013CN202712529U 电连接器组合 The electrical connector assembly
01/30/2013CN202712183U 半导体模块 Semiconductor Modules
01/30/2013CN202712172U Multi-chip dual-base island SOP package structure
01/30/2013CN202712171U Plane compression joint type lead frame for packaging diode
01/30/2013CN202712170U TO247 lead frame
01/30/2013CN202712169U Lead-out electrode structure for large power semiconductor module