| Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155) |
|---|
| 05/21/2013 | US8446004 Power light emitting die package with reflecting lens and the method of making the same |
| 05/21/2013 | US8446003 Semiconductor device including double-sided multi-electrode chip embedded in multilayer wiring substrate |
| 05/21/2013 | US8446002 Multilayer wiring substrate having a castellation structure |
| 05/21/2013 | US8446000 Package structure and package process |
| 05/21/2013 | US8445999 Direct contact leadless package |
| 05/21/2013 | US8445998 Leadframe structures for semiconductor packages |
| 05/21/2013 | US8445997 Stacked packaged integrated circuit devices |
| 05/21/2013 | US8445996 Semiconductor package |
| 05/21/2013 | US8445989 Semiconductor device |
| 05/21/2013 | US8445966 Method and apparatus for protection against process-induced charging |
| 05/21/2013 | US8445921 Thin film light emitting diode |
| 05/21/2013 | US8445907 Semiconductor device including process monitoring pattern having overlapping input/output pad array area |
| 05/21/2013 | US8445906 Method for sorting and acquiring semiconductor element, method for producing semiconductor device, and semiconductor device |
| 05/21/2013 | US8445904 Transparent rectifying metal/metal oxide/semiconductor contact structure and method for the production thereof and use |
| 05/21/2013 | US8445831 Liquid electrical interconnect and devices using same |
| 05/21/2013 | US8445330 Interconnects for packaged semiconductor devices and methods for manufacturing such devices |
| 05/21/2013 | US8445328 Method for producing chip elements equipped with wire insertion grooves |
| 05/21/2013 | US8445322 Method of fabricating semiconductor package |
| 05/21/2013 | US8445305 Method for manufacturing 3-dimensional structures using thin film with columnar nano pores and manufacture thereof |
| 05/21/2013 | US8445094 Circuitized substrate with dielectric layer having dielectric composition not including continuous or semi-continuous fibers |
| 05/21/2013 | US8444988 Cancer treatment method |
| 05/17/2013 | DE202013004256U1 Wärmerohr Heat pipe |
| 05/16/2013 | WO2013071171A1 Low-k dielectric protection spacer for patterning through substrate vias through a low-k wiring layer |
| 05/16/2013 | WO2013070806A1 Voltage switchable dielectric material formations and supporting impedance elements for esd protection |
| 05/16/2013 | WO2013070207A1 Thermal expansion compensators for controlling microelectronic package warpage |
| 05/16/2013 | WO2013069947A1 Tape carrier package and method of manufacturing the same |
| 05/16/2013 | WO2013069327A1 Heat transfer sheet |
| 05/16/2013 | WO2013069277A1 Semiconductor device |
| 05/16/2013 | WO2013069271A1 Polymer structure |
| 05/16/2013 | WO2013069213A1 Wireless apparatus and method for manufacturing same |
| 05/16/2013 | WO2013068146A1 Electronic module for a control unit |
| 05/16/2013 | WO2013068035A1 Interconnect device, electronic device, and method of using a self-heatable conductive path of the interconnect device |
| 05/16/2013 | WO2013068009A1 Power module cooling |
| 05/16/2013 | WO2013068004A1 Heat sink system for an electrical device |
| 05/16/2013 | WO2013067840A1 Method of manufacturing heat sink structure for high-power led |
| 05/16/2013 | WO2013067716A1 Backlight module and display device effecting heat dissipation of led light source |
| 05/16/2013 | WO2013067659A1 Bump structure of wafer bonding pad and manufacturing method thereof |
| 05/16/2013 | WO2013022477A3 Lead carrier with multi-material print formed package components |
| 05/16/2013 | WO2013009866A3 Memory module in a package |
| 05/16/2013 | US20130122655 Embedded Wafer-Level Bonding Approaches |
| 05/16/2013 | US20130122654 Package Substrate Having Die Pad with Outer Raised Portion and Interior Recessed Portion |
| 05/16/2013 | US20130120948 Circuit component and method of making the same |
| 05/16/2013 | US20130120699 Semiconductor device, method of manufacturing the device, and liquid crystal display |
| 05/16/2013 | US20130120021 3d ic structure and method |
| 05/16/2013 | US20130120018 Test Structure and Method of Testing Electrical Characteristics of Through Vias |
| 05/16/2013 | US20130119565 Rotating Curing |
| 05/16/2013 | US20130119564 Epoxy resin composition and semiconductor device |
| 05/16/2013 | US20130119563 Anisotropic conductive film composition and semiconductor device bonded by the same |
| 05/16/2013 | US20130119562 Semiconductor package, semiconductor package manufacturing method and semiconductor device |
| 05/16/2013 | US20130119561 Semiconductor device |
| 05/16/2013 | US20130119560 Packaging structural member |
| 05/16/2013 | US20130119559 Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die |
| 05/16/2013 | US20130119558 Stacked Semiconductor Package |
| 05/16/2013 | US20130119557 Systems comprising a semiconductor device and structure |
| 05/16/2013 | US20130119556 Chip package |
| 05/16/2013 | US20130119555 Through-Package-Via (TPV) Structures On Inorganic Interposer And Methods For Fabricating Same |
| 05/16/2013 | US20130119554 Semiconductor device and method of testing the same |
| 05/16/2013 | US20130119553 Semiconductor package and method of manufacturing the same |
| 05/16/2013 | US20130119552 Method for Forming Chip-on-Wafer Assembly |
| 05/16/2013 | US20130119551 Semiconductor element and fabrication method thereof |
| 05/16/2013 | US20130119550 Semiconductor device and method of manufacturing the same |
| 05/16/2013 | US20130119549 Mold Chase Design for Package-on-Package Applications |
| 05/16/2013 | US20130119548 Method to fabricate high performance carbon nanotube transistor integrated circuits by three-dimensional integration technology |
| 05/16/2013 | US20130119547 Integrated circuit device including through-silicon via structure having offset interface |
| 05/16/2013 | US20130119545 Semiconductor device and method for forming the same |
| 05/16/2013 | US20130119544 Microelectronic package and method of manufacturing same |
| 05/16/2013 | US20130119543 Through silicon via for stacked wafer connections |
| 05/16/2013 | US20130119542 Package having stacked memory dies with serially connected buffer dies |
| 05/16/2013 | US20130119541 Printed circuit board |
| 05/16/2013 | US20130119540 Semiconductor package and method for manufacturing the same |
| 05/16/2013 | US20130119539 Package Structures and Methods for Forming the Same |
| 05/16/2013 | US20130119538 Wafer level chip size package |
| 05/16/2013 | US20130119537 Semiconductor device and method of manufacturing the same |
| 05/16/2013 | US20130119536 Method for forming studs used for self-alignment of solder bumps |
| 05/16/2013 | US20130119535 Flip chip packages with improved thermal performance |
| 05/16/2013 | US20130119534 Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump |
| 05/16/2013 | US20130119533 Package for Three Dimensional Integrated Circuit |
| 05/16/2013 | US20130119532 Bumps for Chip Scale Packaging |
| 05/16/2013 | US20130119531 Semiconductor device and method for manufacturing the same |
| 05/16/2013 | US20130119530 Thermally enhanced packaging structure |
| 05/16/2013 | US20130119529 Semiconductor device having lid structure and method of making same |
| 05/16/2013 | US20130119528 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods |
| 05/16/2013 | US20130119527 Semiconductor die assemblies with enhanced thermal management, semiconductor devices including same and related methods |
| 05/16/2013 | US20130119526 Lead frame, semiconductor manufacturing apparatus, and semiconductor device |
| 05/16/2013 | US20130119525 Power Semiconductor Unit, Power Module, Power Semiconductor Unit Manufacturing Method, and Power Module Manufacturing Method |
| 05/16/2013 | US20130119524 Chip package, method for forming the same, and package wafer |
| 05/16/2013 | US20130119523 Packaging structure and method and electronic device |
| 05/16/2013 | US20130119521 Through-Silicon Via With Low-K Dielectric Liner |
| 05/16/2013 | US20130119520 Chips with high fracture toughness through a metal ring |
| 05/16/2013 | US20130119517 Plasma Dicing and Semiconductor Devices Formed Thereof |
| 05/16/2013 | US20130119510 Devices including a p-i-n diode disposed adjacent a silicide in series with a dielectric material |
| 05/16/2013 | US20130119509 Forming beol line fuse structure |
| 05/16/2013 | US20130119506 Formation of sti trenches for limiting pn-junction leakage |
| 05/16/2013 | US20130119472 Semiconductor device |
| 05/16/2013 | US20130119461 Semiconductor device having a buried gate and method for forming thereof |
| 05/16/2013 | US20130119435 Dielectric dummification for enhanced planarization with spin-on dielectrics |
| 05/16/2013 | US20130119404 Device structure including high-thermal-conductivity substrate |
| 05/16/2013 | US20130119382 Plating Process and Structure |
| 05/16/2013 | US20130119118 Method for manufacturing semiconductor laser apparatus, semiconductor laser apparatus, and optical apparatus |
| 05/16/2013 | US20130119117 Bonding wedge |