| Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155) |
|---|
| 06/18/2013 | US8466561 Semiconductor module with a power semiconductor chip and a passive component and method for producing the same |
| 06/18/2013 | US8466560 Dummy structures having a golden ratio and method for forming the same |
| 06/18/2013 | US8466559 Forming die backside coating structures with coreless packages |
| 06/18/2013 | US8466557 Solder bump confinement system for an integrated circuit package |
| 06/18/2013 | US8466555 Gold-free ohmic contacts |
| 06/18/2013 | US8466554 Electronic device having interconnections, openings, and pads having greater width than the openings |
| 06/18/2013 | US8466553 Semiconductor device and semiconductor package having the same |
| 06/18/2013 | US8466552 Semiconductor device and method of manufacturing the same |
| 06/18/2013 | US8466551 Semiconductor device |
| 06/18/2013 | US8466550 Semiconductor structure and a method of manufacturing a semiconductor structure |
| 06/18/2013 | US8466549 Semiconductor device for power conversion |
| 06/18/2013 | US8466548 Semiconductor device including excess solder |
| 06/18/2013 | US8466547 Method for manufacturing substrate for semiconductor element, and semiconductor device |
| 06/18/2013 | US8466546 Chip-scale package |
| 06/18/2013 | US8466545 Stackable semiconductor package |
| 06/18/2013 | US8466544 Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of Fo-WLCSP |
| 06/18/2013 | US8466543 Three dimensional stacked package structure |
| 06/18/2013 | US8466542 Stacked microelectronic assemblies having vias extending through bond pads |
| 06/18/2013 | US8466541 Low inductance power module |
| 06/18/2013 | US8466540 Semiconductor device and manufacturing method therefor |
| 06/18/2013 | US8466539 MRAM device and method of assembling same |
| 06/18/2013 | US8466526 Hall sensor for eliminating offset voltage |
| 06/18/2013 | US8466468 Organic el display panel and method of manufacturing the same |
| 06/18/2013 | US8466464 Test and enable circuitry connected between embedded die circuits |
| 06/18/2013 | US8466377 Electronic device housing |
| 06/18/2013 | US8466060 Stackable power MOSFET, power MOSFET stack, and process of manufacture |
| 06/18/2013 | US8466055 Semiconductor device and method of manufacturing semiconductor device |
| 06/18/2013 | US8466010 Seal ring support for backside illuminated image sensor |
| 06/18/2013 | US8466009 Method of fabricating a semiconductor package with mold lock opening |
| 06/18/2013 | US8465994 Method for fabricating active-matrix display device |
| 06/18/2013 | US8465837 Epoxy resin composition, prepreg, laminate board, multilayer printed wiring board, semiconductor device, insulating resin sheet, and process for manufacturing multilayer printed wiring board |
| 06/18/2013 | US8465666 Thermoconductive composition, heat dissipating plate, heat dissipating substrate and circuit module using thermoconductive composition, and process for production of thermoconductive composition |
| 06/18/2013 | US8464781 Cooling systems incorporating heat exchangers and thermoelectric layers |
| 06/18/2013 | US8464780 Heat sink with heat pipes and method for manufacturing the same |
| 06/18/2013 | DE202013005091U1 Kühlmodul Cooling module |
| 06/18/2013 | CA2454895C Methods of nanotube films and articles |
| 06/13/2013 | WO2013086454A1 Led bulb with liquid-cooled drive electronics |
| 06/13/2013 | WO2013086047A1 Integrated multi-chip module optical interconnect platform |
| 06/13/2013 | WO2013085815A1 Antifuse-based memory cells having multiple memory states and methods of forming the same |
| 06/13/2013 | WO2013085618A1 Design of a heat dissipation structure for an integrated circuit (ic) chip |
| 06/13/2013 | WO2013085542A1 Reducing dielectric loss in solder masks |
| 06/13/2013 | WO2013085497A1 Semiconductor chip stacking assemblies |
| 06/13/2013 | WO2013085492A1 Shaped and oriented solder joints |
| 06/13/2013 | WO2013085465A1 Apparatus for heat dissipation and a method for fabricating the apparatus |
| 06/13/2013 | WO2013084842A1 Led package and production method for led package |
| 06/13/2013 | WO2013084836A1 Sheet-shaped coupling agent, coupling method, and manufacturing method for electronic device |
| 06/13/2013 | WO2013084589A1 Semiconductor device and semiconductor device manufacturing method |
| 06/13/2013 | WO2013084479A1 Wireless module |
| 06/13/2013 | WO2013084417A1 Power conversion apparatus |
| 06/13/2013 | WO2013084334A1 Substrate for large-capacity module, and manufacturing method for said substrate |
| 06/13/2013 | WO2013083714A1 An interposer device |
| 06/13/2013 | WO2013082970A1 Dense-pitch small-pad copper wire bonded double ic chip stack packaging piece and preparation method therefor |
| 06/13/2013 | WO2013082844A1 Interconnection structure and method for fabricating the same |
| 06/13/2013 | WO2013082834A1 Resistance test structure and method |
| 06/13/2013 | WO2013055453A3 Solder-coated copper stud bump wafer level package and manufacturing method thereof |
| 06/13/2013 | WO2013019040A3 Photo-curable organic-inorganic hybrid resin composition |
| 06/13/2013 | WO2013016335A3 Lead frameless hermetic circuit package |
| 06/13/2013 | US20130149857 Solder interconnect by addition of copper |
| 06/13/2013 | US20130147510 Monitoring testkey used in semiconductor fabrication |
| 06/13/2013 | US20130147509 Test pattern of semiconductor device, method of manufacturing test pattern and method of testing semiconductor device by using test pattern |
| 06/13/2013 | US20130147067 Locally tailoring chemical mechanical polishing (cmp) polish rate for dielectrics |
| 06/13/2013 | US20130147066 Structure and method for e-beam in-chip overlay mark |
| 06/13/2013 | US20130147065 Semiconductor Device and Method of Forming Adjacent Channel and Dam Material Around Die Attach Area of Substrate to Control Outward Flow of Underfill Material |
| 06/13/2013 | US20130147064 Semiconductor device |
| 06/13/2013 | US20130147062 Multi-chip package and method of manufacturing the same |
| 06/13/2013 | US20130147061 Trap Rich Layer with Through-Silicon-Vias in Semiconductor Devices |
| 06/13/2013 | US20130147060 Semiconductor package |
| 06/13/2013 | US20130147059 Chip-to-wafer bonding method and three-dimensional integrated semiconductor device |
| 06/13/2013 | US20130147058 Chip package and chip package method |
| 06/13/2013 | US20130147057 Through silicon via (tsv) isolation structures for noise reduction in 3d integrated circuit |
| 06/13/2013 | US20130147055 Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV through Semiconductor Wafer |
| 06/13/2013 | US20130147054 Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP |
| 06/13/2013 | US20130147053 Semiconductor Device and Method of Making Single Layer Substrate with Asymmetrical Fibers and Reduced Warpage |
| 06/13/2013 | US20130147052 Offset of contact opening for copper pillars in flip chip packages |
| 06/13/2013 | US20130147051 Method of protecting against via failure and structure therefor |
| 06/13/2013 | US20130147050 Semiconductor having integrally-formed enhanced thermal management |
| 06/13/2013 | US20130147049 Circuit Probing Structures and Methods for Probing the Same |
| 06/13/2013 | US20130147048 Integrated circuit devices including electrode support structures and methods of fabricating the same |
| 06/13/2013 | US20130147047 Integrated Circuit and Method of Forming an Integrated Circuit |
| 06/13/2013 | US20130147046 Integrated Technology for Partial Air Gap Low K Deposition |
| 06/13/2013 | US20130147045 Flash Memory Having Multi-Level Architecture |
| 06/13/2013 | US20130147044 Multi-chip package having a stacked plurality of different sized semiconductor chips, and method of manufacturing the same |
| 06/13/2013 | US20130147043 Substrate with embedded stacked through-silicon via die |
| 06/13/2013 | US20130147042 Semiconductor device |
| 06/13/2013 | US20130147041 Stack package structure and fabrication method thereof |
| 06/13/2013 | US20130147040 Mems chip scale package |
| 06/13/2013 | US20130147039 Semiconductor device |
| 06/13/2013 | US20130147038 Semiconductor device including stacked semiconductor chips without occurring of crack |
| 06/13/2013 | US20130147037 Semiconductor structure |
| 06/13/2013 | US20130147036 Semiconductor Device and Method of Forming UBM Structure on Back Surface of TSV Semiconductor Wafer |
| 06/13/2013 | US20130147035 Semiconductor Device and Method of Forming Recesses in Conductive Layer to Detect Continuity for Interconnect Between Semiconductor Die and Substrate |
| 06/13/2013 | US20130147034 Bump structure design for stress reduction |
| 06/13/2013 | US20130147033 Post-passivation interconnect structure |
| 06/13/2013 | US20130147032 Passivation layer for packaged chip |
| 06/13/2013 | US20130147031 Semiconductor device with bump structure on post-passivation interconncet |
| 06/13/2013 | US20130147030 Landing Areas of Bonding Structures |
| 06/13/2013 | US20130147029 Ultra-small chip package and method for manufacturing the same |
| 06/13/2013 | US20130147028 Heat spreader for multiple chip systems |
| 06/13/2013 | US20130147027 Semiconductor package |
| 06/13/2013 | US20130147026 Heatsink interposer |