Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
08/2013
08/28/2013CN102376660B Radiating device
08/28/2013CN102290399B Stacking type chip packaging structure and method
08/28/2013CN102214623B Chip package and method for forming the same
08/28/2013CN102208383B Circuit board and formation method thereof
08/28/2013CN102165584B Input/output architecture for mounted processors, and methods of using same
08/28/2013CN102157453B Stack-type package structure and manufacturing method thereof
08/28/2013CN102074498B Integrated circuits and methods for forming the integrated circuits
08/28/2013CN101958312B Electronic control unit
08/28/2013CN101887869B Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package
08/28/2013CN101755336B Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
08/28/2013CN101685818B 半导体器件 Semiconductor devices
08/28/2013CN101635288B System with power semiconductor module and connection device
08/28/2013CN101635287B 功率半导体模块 Power semiconductor module
08/28/2013CN101438401B Aluminum-silicon carbide composite body and method for processing the same
08/28/2013CN101317264B Improved heat sink assembly
08/28/2013CA2807715A1 Method of arranging ring segments on a wafer for functionalized layers of an ophthalmic lens
08/27/2013US8519552 Chip structure
08/27/2013US8519551 Semiconductor device with I/O cell and external connection terminal and method of manufacturing the same
08/27/2013US8519549 Anisotropic conductive film and display device having the same
08/27/2013US8519548 Wafer level packaged GaN power device and the manufacturing method thereof
08/27/2013US8519547 Chip arrangement and method for producing a chip arrangement
08/27/2013US8519546 Stacked multi-die electronic device with interposed electrically conductive strap
08/27/2013US8519544 Semiconductor device and method of forming WLCSP structure using protruded MLP
08/27/2013US8519543 Large sized silicon interposers overcoming the reticle area limitations
08/27/2013US8519542 Air through-silicon via structure
08/27/2013US8519541 Semiconductor device having plural conductive layers disposed within dielectric layer
08/27/2013US8519540 Self-aligned dual damascene BEOL structures with patternable low- K material and methods of forming same
08/27/2013US8519539 Metal wire for a semiconductor device formed with a metal layer without voids therein and a method for forming the same
08/27/2013US8519537 3D semiconductor package interposer with die cavity
08/27/2013US8519536 Semiconductor device including bump formed on substrate to prevent extremely-low dielectric constant (ELK) interlayer dielectric layer (ILD) delamination during reflow process
08/27/2013US8519535 Method and structure for controlling package warpage
08/27/2013US8519534 Microsprings partially embedded in a laminate structure and methods for producing same
08/27/2013US8519533 Semiconductor device including a DC-DC converter with schottky barrier diode
08/27/2013US8519532 Semiconductor device including cladded base plate
08/27/2013US8519531 Electrical and/or electronic device with elastic contact element
08/27/2013US8519530 Method for treating nanofiber material and composition of nanofiber material
08/27/2013US8519529 Semiconductor package with lid bonded on wiring board and method of manufacturing the same
08/27/2013US8519528 Semiconductor structure and method for interconnection of integrated circuits
08/27/2013US8519526 Semiconductor package and fabrication method thereof
08/27/2013US8519525 Semiconductor encapsulation and method thereof
08/27/2013US8519524 Chip stacking structure and fabricating method of the chip stacking structure
08/27/2013US8519523 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
08/27/2013US8519522 Semiconductor package
08/27/2013US8519521 Electronic device including a packaging substrate having a trench
08/27/2013US8519520 Semiconductor package of small footprint with a stack of lead frame die paddle sandwich between high-side and low-side MOSFETs and manufacturing method
08/27/2013US8519519 Semiconductor device having die pads isolated from interconnect portion and method of assembling same
08/27/2013US8519518 Integrated circuit packaging system with lead encapsulation and method of manufacture thereof
08/27/2013US8519517 Semiconductor system with fine pitch lead fingers and method of manufacturing thereof
08/27/2013US8519516 Semiconductor constructions
08/27/2013US8519513 Semiconductor wafer plating bus
08/27/2013US8519512 Test line placement to improve die sawing quality
08/27/2013US8519507 Electrically programmable fuse using anisometric contacts and fabrication method
08/27/2013US8519493 Semiconductor device having multiple substrates
08/27/2013US8519480 Electrostatic discharge protection device
08/27/2013US8519457 Solid-state image pickup device and a camera module
08/27/2013US8519453 Thin film transistor device with metallic electrodes
08/27/2013US8519434 Self detection device for high voltage ESD protection
08/27/2013US8519391 Semiconductor chip with backside conductor structure
08/27/2013US8519390 Test pattern for measuring semiconductor alloys using X-ray Diffraction
08/27/2013US8519389 Semiconductor device, method of manufacturing the same, and method of designing the same
08/27/2013US8519388 Embedded structure for passivation integrity testing
08/27/2013US8519277 Surface mounted electronic component
08/27/2013US8519256 Thermoelectric material, thermoelectric element, thermoelectric module and method for manufacturing the same
08/27/2013US8519067 Epoxy resin composition and semiconductor device
08/27/2013US8518825 Method to manufacture trench-first copper interconnection
08/27/2013US8518823 Through silicon via and method of forming the same
08/27/2013US8518819 Semiconductor device contact structures and methods for making the same
08/27/2013US8518752 Integrated circuit packaging system with stackable package and method of manufacture thereof
08/27/2013US8518749 Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die
08/27/2013US8518303 Adhesive composition, circuit connecting material, connection structure of circuit member, and semiconductor device
08/27/2013US8517264 Smart cards and user terminals including the same
08/23/2013DE202013007254U1 Vapor-Chamber-Kühler Vapor Chamber cooler
08/22/2013WO2013123435A1 Heat spreading substrate with embedded interconnects
08/22/2013WO2013123259A2 Maintaining alignment in a multi-chip module using a compressible structure
08/22/2013WO2013122734A1 Flexible metallic heat connector
08/22/2013WO2013122551A1 Method and device for testing and adjusting the temperature coefficient of integrated circuits
08/22/2013WO2013121882A1 Circuit board for mounting electronic components
08/22/2013WO2013095405A9 Enabling package-on-package (pop) pad surface finishes on bumpless build-up layer (bbul) package
08/22/2013WO2013095147A4 Method of bonding two substrates and device manufactured thereby
08/22/2013WO2013052398A3 Stub minimization for assemblies without wirebonds to package substrate
08/22/2013US20130217188 Structures and Formation Methods of Packages with Heat Sinks
08/22/2013US20130217183 Stacked microfeature devices and associated methods
08/22/2013US20130217182 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
08/22/2013US20130214855 Integrated Circuit Die Stacks With Rotationally Symmetric VIAS
08/22/2013US20130214435 Epoxy encapsulating and lamination adhesive and method of making same
08/22/2013US20130214434 Semiconductor device and manufacturing method thereof
08/22/2013US20130214433 Efficient Non-Integral Multi-Height Standard Cell Placement
08/22/2013US20130214432 Stacked die assembly
08/22/2013US20130214430 Integrated circuit packaging system with formed under-fill and method of manufacture thereof
08/22/2013US20130214429 Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers
08/22/2013US20130214428 Semiconductor device having non-planar interface between a plug layer and a contact layer
08/22/2013US20130214427 Semiconductor device having plural semiconductor chips stacked with each other
08/22/2013US20130214426 Semiconductor Package Including an Organic Substrate and Interposer Having Through-Semiconductor Vias
08/22/2013US20130214425 Dual side package on package
08/22/2013US20130214424 Structure and manufacturing method for reducing stress of chip
08/22/2013US20130214423 Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices
08/22/2013US20130214421 Disabling electrical connections using pass-through 3d interconnects and associated systems and methods
08/22/2013US20130214420 Semiconductor device
08/22/2013US20130214419 Semiconductor packaging method and structure thereof
08/22/2013US20130214418 Semiconductor Device Package with Slanting Structures