Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 23 - Details of semiconductor or other solid state devices
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
10/2013
10/01/2013US8546932 Thin substrate PoP structure
10/01/2013US8546931 Stacked semiconductor components having conductive interconnects
10/01/2013US8546930 3-D ICs equipped with double sided power, coolant, and data features
10/01/2013US8546929 Embedded integrated circuit package-on-package system
10/01/2013US8546928 Micromechanical housing comprising at least two cavities having different internal pressure and/or different gas compositions and method for the production thereof
10/01/2013US8546927 RFIC chip mounting structure
10/01/2013US8546926 Power converter
10/01/2013US8546925 Synchronous buck converter having coplanar array of contact bumps of equal volume
10/01/2013US8546924 Package structures for integrating thermoelectric components with stacking chips
10/01/2013US8546923 Rigid power module suited for high-voltage applications
10/01/2013US8546922 Wiring board
10/01/2013US8546921 Hybrid multilayer substrate
10/01/2013US8546920 Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)
10/01/2013US8546913 Semiconductor integrated circuit device
10/01/2013US8546909 Nonvolatile semiconductor memory device having air gap proximate to element isolation region and method of manufacturing the same
10/01/2013US8546885 Metal gate electrode of a field effect transistor
10/01/2013US8546884 High value resistors in gallium arsenide
10/01/2013US8546802 Pick-and-place tool for packaging process
10/01/2013US8546801 Semiconductor apparatus manufacturing method and semiconductor apparatus
10/01/2013US8546732 Heating plate with planar heater zones for semiconductor processing
10/01/2013US8546276 Deposition of group IV metal-containing films at high temperature
10/01/2013US8546253 Self-aligned polymer passivation/aluminum pad
10/01/2013US8546195 Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor
10/01/2013US8546193 Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and interconnect structure
10/01/2013US8546189 Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection
10/01/2013US8546188 Bow-balanced 3D chip stacking
10/01/2013US8545998 Electroless deposition of platinum on copper
10/01/2013US8545987 Thermal interface material with thin transfer film or metallization
10/01/2013CA2454845C Nanotube films and articles
09/2013
09/26/2013WO2013142867A1 Packaged semiconductor device having multilevel leadframes configured as modules
09/26/2013WO2013142484A2 Apparatus and method for remotely determining the structural intergrity of a well or similar structure
09/26/2013WO2013142294A1 Micro-link high-bandwidth chip-to-chip bus
09/26/2013WO2013142240A1 Compositions of resin-linear organosiloxane block copolymers
09/26/2013WO2013142156A1 Direct growth of diamond in backside vias for gan hemt devices
09/26/2013WO2013142140A1 Process for preparing resin- linear organosiloxane block copolymers
09/26/2013WO2013142138A1 Compositions of resin-linear organosiloxane block copolymers
09/26/2013WO2013142112A1 Integrated circuit package having a split lead frame
09/26/2013WO2013141701A1 An assembly and a chip package
09/26/2013WO2013141360A1 Curable composition, cured product, and method for using curable composition
09/26/2013WO2013141330A1 Electroconductive thin film, coating liquid for forming electroconductive thin film, field-effect transistor, and method for producing field-effect transistor
09/26/2013WO2013141287A1 Semiconductor device and method for manufacturing same
09/26/2013WO2013141247A1 Active ester resin, thermosetting resin composition, cured product of same, semiconductor encapsulation material, prepreg, circuit board, and build-up film
09/26/2013WO2013141154A1 Semiconductor module having heat dissipating fin
09/26/2013WO2013141110A1 Method for manufacturing substrate with integrated radiator, and substrate with integrated radiator
09/26/2013WO2013141013A1 Element-accommodating package
09/26/2013WO2013140928A1 Semiconductor device
09/26/2013WO2013140886A1 Semiconductor device and semiconductor module
09/26/2013WO2013140761A1 Cooling structure for electronic substrate, and electronic device using same
09/26/2013WO2013140741A1 Thermally conductive body and electronic device using same
09/26/2013WO2013140724A1 Method for producing graphite sheet
09/26/2013WO2013140704A1 Power conversion apparatus
09/26/2013WO2013140703A1 Power conversion device
09/26/2013WO2013140663A1 Semiconductor module and method for manufacturing same
09/26/2013WO2013140654A1 Semiconductor module
09/26/2013WO2013140503A1 Semiconductor device and semiconductor system
09/26/2013WO2013140449A1 Cover assembly for electronic component, electronic component using same, and method for manufacturing electronic component
09/26/2013WO2013140295A2 Thermal interface material
09/26/2013WO2013140226A2 System and method for controlling internal temperature of electronic components
09/26/2013WO2013140094A1 Method for producing at least one pad assembly on a support for the self-assembly of an integrated circuit chip on the support by the formation of a fluorinated material surrounding the pad and exposure of the pad and the fluorinated material to an ultraviolet treatment in the presence of ozone
09/26/2013WO2013139058A1 Thermal dissipation substrate and manufacturing method therefor
09/26/2013US20130254448 Micro-link high-bandwidth chip-to-chip bus
09/26/2013US20130252375 Magnet Assisted Alignment Method for Wafer Bonding and Wafer Level Chip Scale Packaging
09/26/2013US20130251985 Laminate
09/26/2013US20130251313 High-frequency transmission module and optical connector
09/26/2013US20130250527 Electronic device
09/26/2013US20130249589 Interposer and electrical testing method thereof
09/26/2013US20130249532 Probing Chips during Package Formation
09/26/2013US20130249118 Integrated circuit packaging system with a grid array with a leadframe and method of manufacture thereof
09/26/2013US20130249117 Integrated circuit packaging system with ultra-thin chip and method of manufacture thereof
09/26/2013US20130249116 Microelectronic package
09/26/2013US20130249115 Semiconductor Method and Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
09/26/2013US20130249114 Semiconductor memory device and method of manufacturing the same
09/26/2013US20130249113 Semiconductor memory device
09/26/2013US20130249112 Passive within via
09/26/2013US20130249111 Semiconductor Device and Method of Forming RDL Wider than Contact Pad Along First Axis and Narrower than Contact Pad along Second Axis
09/26/2013US20130249110 Method and apparatus for reduced parasitics and improved multi-finger transistor thermal impedance
09/26/2013US20130249109 Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips
09/26/2013US20130249108 Semiconductor packages, electronic systems employing the same and methods of manufacturing the same
09/26/2013US20130249107 Multi-chip semiconductor apparatus
09/26/2013US20130249106 Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mechanical Support Layer
09/26/2013US20130249105 Semiconductor Device and Method of Forming Micro-Vias Partially through Insulating Material over Bump Interconnect Conductive Layer for Stress Relief
09/26/2013US20130249104 Semiconductor Device and Method of Forming Conductive Layer Over Metal Substrate for Electrical Interconnect of Semiconductor Die
09/26/2013US20130249103 Semiconductor device
09/26/2013US20130249102 Semiconductor device with strengthened inter-wire air gap structures
09/26/2013US20130249101 Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
09/26/2013US20130249100 Power semiconductor device module
09/26/2013US20130249099 Techniques to Form Uniform and Stable Silicide
09/26/2013US20130249098 Protective layer for protecting tsv tips during thermo-compressive bonding
09/26/2013US20130249097 Schemes for Forming Barrier Layers for Copper in Interconnect Structures
09/26/2013US20130249096 Through silicon via filling
09/26/2013US20130249095 Gallium arsenide devices with copper backside for direct die solder attach
09/26/2013US20130249093 Conductive film and semiconductor device
09/26/2013US20130249092 Packaged microelectronic devices recessed in support member cavities, and associated methods
09/26/2013US20130249091 Multi-Direction Design for Bump Pad Structures
09/26/2013US20130249090 Semiconductor Device and Method of Forming Partially-Etched Conductive Layer Recessed Within Substrate for Bonding to Semiconductor Die
09/26/2013US20130249089 Method for manufacturing fine-pitch bumps and structure thereof
09/26/2013US20130249088 Adaptive patterning for panelized packaging
09/26/2013US20130249087 Electronic component and manufacture method thereof
09/26/2013US20130249086 Chip structure, chip bonding structure using the same, and manufacturing method thereof
09/26/2013US20130249085 Semiconductor device having penetrating electrodes each penetrating through semiconductor chip
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