Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
02/2001
02/27/2001US6194246 Process for fabricating electronic devices having a thermally conductive substrate
02/27/2001US6194238 Method of manufacturing photosensitive semiconductor device
02/27/2001US6194235 Method of fabricating and testing an embedded semiconductor device
02/27/2001US6194233 Integrated circuit and method of manufacture for avoiding damage by electrostatic charge
02/27/2001US6194063 Heat-conductive and pressure-sensitive adhesive sheets and method for fixing electronic parts to heat-radiating members with the use of the same
02/27/2001US6194053 Apparatus and method fabricating buried and flat metal features
02/27/2001US6193908 Electroluminescent phosphor powders, methods for making phosphor powders and devices incorporating same
02/27/2001US6193905 Mixture of low boiling perfluorodecahydrophenanthracene and high boiling tris(perfluoro(hexyl or pentyl)) amine; semiconductor cooling
02/27/2001US6193525 Socket for electrical parts
02/27/2001US6193205 Retainer for a BGA fan
02/27/2001US6192956 Method and apparatus for application of spray adhesive to a leadframe for chip bonding
02/27/2001US6192709 Quencher clamping operation using an electromagnet
02/27/2001US6192581 Method of making printed circuit board
02/27/2001US6192579 Tape carrier and manufacturing method therefor
02/27/2001US6192578 Method for electrically coupling bond pads of a microelectronic device
02/22/2001WO2001013436A1 Passivation of gan based fets
02/22/2001WO2001013433A1 Spherical shaped integrated circuit utilizing an inductor
02/22/2001WO2001013431A1 Apparatuses for forming wire bonds from circuitry on a substrate to a semiconductor chip, and methods of forming semiconductor chip assemblies
02/22/2001WO2001013430A1 Heat sink including a heat dissipating fin and method for fixing the heat dissipating fin
02/22/2001WO2001013427A1 Method for contact size control for nand technology
02/22/2001WO2001013426A1 Method of producing copper features on semiconductor wafers
02/22/2001WO2001013416A1 Method and apparatus for depositing and controlling the texture of a thin film
02/22/2001WO2001013384A1 Inductor element
02/22/2001WO2001012695A1 Phenolic resin, epoxy resin, and processes for producing these
02/22/2001WO2000005747A3 Metallization structures for microelectronic applications and process for forming the structures
02/22/2001WO1999064195A3 Curved ceramic moulded part
02/22/2001DE19936322A1 Kratzfeste Beschichtung für Halbleiterbauelemente Scratch resistant coating for semiconductor devices
02/22/2001DE19936321A1 Semiconductor chip testing device for quality control check
02/22/2001DE10040143A1 Resonator for band-pass filter has two similar conductor patterns facing each other on two dielectric substrates joined by adhesive layer
02/22/2001DE10040142A1 Circuit element for band-pass filter on printed circuit board, has ground conductor with conductive members arranged to achieve desired frequency characteristic
02/22/2001DE10002639A1 Bandträger für einen BGA und eine Halbleitervorrichtung, die diesen benutzt Band carrier for BGA and a semiconductor device using this
02/22/2001CA2349568A1 Heat sink including a heat dissipating fin and method for fixing the heat dissipating fin
02/21/2001EP1077502A2 MMIC-to-waveguide RF transition and associated method
02/21/2001EP1077494A2 Heterojunction bipolar transistor and method for fabricating the same
02/21/2001EP1077491A2 Ceramic package for semiconductor device
02/21/2001EP1077490A1 Improvements in or relating to integrated circuit dies
02/21/2001EP1077489A1 Integrated circuit die including conductive pads
02/21/2001EP1077486A1 Semiconductor device
02/21/2001EP1077485A2 Method to deposit a platinum seed layer for use in selective copper plating
02/21/2001EP1077484A2 Barrier layer for electroplating processes
02/21/2001EP1077483A2 Method of making an integrated circuit device having a planar interlevel dielectric layer
02/21/2001EP1077482A2 Semiconductor contacting device
02/21/2001EP1077481A2 Etching aluminium over refractory metal with successive plasmas
02/21/2001EP1076930A1 Surface acoustic wave device package and method
02/21/2001EP1076915A1 Chip stack and method of making same
02/21/2001EP1076913A1 Flip chip with integrated flux, mask and underfill
02/21/2001EP1016139A4 Rf power device having voltage controlled linearity
02/21/2001CN2420784Y Rubber casing structure of bridge rectifier
02/21/2001CN2420730Y Matrix ball arranged packed integrated circuit base device
02/21/2001CN1284790A Surface acoustic wave device suitable for installing flip-chip
02/21/2001CN1284789A Electronic element with conductor and lead terminal
02/21/2001CN1284761A Monolithic microwave integrated circuit-waveguide radio frequency transistion structure and correlation method
02/21/2001CN1284746A Electronic Package for electronic element and manufacturing method thereof
02/21/2001CN1284521A Aromatic ester compound and its prep., expoxy resin composition using the same and coper-coated laminate
02/21/2001CN1284520A Arylester compound and its prep, epoxy resin composition using the compound and copper-coated laminated
02/20/2001USRE37059 Wiring pattern of semiconductor integrated circuit device
02/20/2001US6192431 Method and apparatus for configuring the pinout of an integrated circuit
02/20/2001US6191952 Compliant surface layer for flip-chip electronic packages and method for forming same
02/20/2001US6191946 Heat spreader with excess solder basin
02/20/2001US6191945 Cold plate arrangement for cooling processor and companion voltage regulator
02/20/2001US6191944 Heat sink for electric and/or electronic devices
02/20/2001US6191602 Wafer acceptance testing method and structure of a test key used in the method
02/20/2001US6191495 Micromagnetic device having an anisotropic ferromagnetic core and method of manufacture therefor
02/20/2001US6191494 Semiconductor device and method of producing the same
02/20/2001US6191493 Resin seal semiconductor package and manufacturing method of the same
02/20/2001US6191492 Electronic device including a densified region
02/20/2001US6191491 Semiconductor integrated circuit device
02/20/2001US6191490 Semiconductor package having a separated die pad
02/20/2001US6191489 Micromechanical layer stack arrangement particularly for flip chip or similar connections
02/20/2001US6191488 Flip chip type semiconductor package and method of injecting resin into device thereof
02/20/2001US6191487 Semiconductor and flip chip packages and method having a back-side connection
02/20/2001US6191486 Technique for producing interconnecting conductive links
02/20/2001US6191485 Semiconductor device
02/20/2001US6191483 Package structure for low cost and ultra thin chip scale package
02/20/2001US6191482 Semiconductor chip carrier having partially buried conductive pattern and semiconductor device using the same
02/20/2001US6191481 Electromigration impeding composite metallization lines and methods for making the same
02/20/2001US6191480 Universal land grid array socket engagement mechanism
02/20/2001US6191479 Decoupling capacitor configuration for integrated circuit chip
02/20/2001US6191478 Demountable heat spreader and high reliability flip chip package assembly
02/20/2001US6191477 Leadless chip carrier design and structure
02/20/2001US6191476 Semiconductor device
02/20/2001US6191475 Substrate for reducing electromagnetic interference and enclosure
02/20/2001US6191474 Vertically mountable interposer assembly and method
02/20/2001US6191473 Bonding lead structure with enhanced encapsulation
02/20/2001US6191472 Hole geometry of a semiconductor package substrate
02/20/2001US6191468 Inductor with magnetic material layers
02/20/2001US6191434 Semiconductor device measuring socket having socket position adjustment member
02/20/2001US6191370 Ball grid array semiconductor package and method of fabricating the same
02/20/2001US6191368 Flexible, releasable strip leads
02/20/2001US6191367 Wiring construction body with conductive lines in a resin binder
02/20/2001US6191366 Board for IC card having component mounting recess
02/20/2001US6191360 Thermally enhanced BGA package
02/20/2001US6191359 Mass reflowable windowed package
02/20/2001US6191036 Use of photoresist focus exposure matrix array as via etch monitor
02/20/2001US6191033 Covering with a titanium layer the surfaces of a dielectric film having contact opening through to doped substrate, oxidizing titanium, annealing in a nitriding atmosphere, then forming second oxidized titanium layer and annealing again
02/20/2001US6191032 Thin titanium film as self-regulating filter for silicon migration into aluminum metal lines
02/20/2001US6191031 Process for producing multi-layer wiring structure
02/20/2001US6191027 Method of forming flat wiring layer
02/20/2001US6191024 Apparatus and method for manufacturing a semiconductor package
02/20/2001US6191023 Method of improving copper pad adhesion