Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
05/2001
05/29/2001US6238469 Dual-valent rare earth additives to polishing slurries
05/29/2001US6238454 Heat-dissipating microcircuit packaging composite having similar coefficient of thermal expansion as microcircuit and comprising powder metallurgically formed, sintered mixture of copper, carbon and wetting agent metals which form carbides
05/29/2001US6238223 Method of depositing a thermoplastic polymer in semiconductor fabrication
05/29/2001US6238181 Heat dissipating device for portable apparatus
05/29/2001US6238086 Method of calculating thermal resistance in semiconductor package accommodating semiconductor chip within a case which can be applied to calculation for semiconductor package with radiation fins
05/29/2001US6237682 Cooling module including a pressure relief mechanism
05/29/2001US6237223 Method of forming a phase change heat sink
05/29/2001US6237222 Method of producing a radiator and product thereof
05/29/2001CA2202576C Electronic circuit assembly
05/25/2001WO2001037621A2 Method for producing a support element for an integrated circuit (ic) component
05/25/2001WO2001037376A1 Arrangement for electrically connecting chips in a circuit that is embodied in a three-dimensional manner
05/25/2001WO2001037341A1 Multichip ic-card comprising a bus structure
05/25/2001WO2001037340A1 Programmable semiconductor device structures and methods for making the same
05/25/2001WO2001037339A1 Air gap dielectric in self-aligned via structures
05/25/2001WO2001037338A2 Method for integrating a chip in a printed board and integrated circuit
05/25/2001WO2001037337A1 Ball grid substrate for lead-on-chip semiconductor package
05/25/2001WO2001037336A1 Multi-chip module for use in high-power applications
05/25/2001WO2001037335A2 Packaging for a semiconductor chip
05/25/2001WO2001037323A2 Vertical transformer
05/25/2001WO2001037322A2 System and method for product yield prediction using a logic characterization vehicle
05/25/2001WO2001037288A1 An arrangement for electrically insulating a high voltage component
05/25/2001WO2001037285A1 Method for testing semiconductor memory
05/25/2001WO2001037150A1 System and method for product yield prediction using device and process neighborhood characterization vehicle
05/25/2001WO2001036992A1 The passive multiplexor test structure for intergrated circuit manufacturing
05/25/2001WO2001036990A2 Wafer level interposer
05/25/2001WO2001036917A1 Integrated circuit device and correction method for integrated circuit device
05/25/2001WO2001036349A1 Method for attaching a body, which is comprised of a metal matrix composite (mmc) material, to a ceramic body
05/25/2001WO2001035718A2 System and method for product yield prediction
05/25/2001WO2001011661A3 Passive electrical components formed on carbon coated insulating substrates
05/25/2001WO2000063950A3 Sub-package bypass capacitor mounting for an array packaged integrated circuit
05/24/2001US20010001741 Process for the production of semiconductor device
05/24/2001US20010001740 Semiconductor encapsulated in a hollow package, made by housing a chip in a plurality of cavities of a plate-like substrate, bonding a plate-like cap to teh substrate, and separating the bonded members along space between cavities
05/24/2001US20010001735 Method for restoring an alignment mark after planarization of a dielectric layer
05/24/2001US20010001727 By forming a protective film on the surface by High-Density Plasma Chemical Vapor Deposition; better filling of gaps between metal lines
05/24/2001US20010001714 Forming electronic circuit on wafer in region defined by scribe line, attaching circuit substrate carrying predetermined conductor pattern on wafer, interconnecting by wire bonding, forming spherical electrode, dicing
05/24/2001US20010001594 Electronic package with stacked connections and method for making same
05/24/2001US20010001593 Electronic package with stacked connections and method for making same
05/24/2001US20010001592 Lossy RF shield for integrated circuits
05/24/2001US20010001507 Substrate for a semiconductor device, a semiconductor device, a card type module, and a data memory device
05/24/2001US20010001506 Method of forming contact openings
05/24/2001US20010001505 Tape ball grid array with interconnected ground plane
05/24/2001US20010001504 Semiconductor device
05/24/2001US20010001503 Contact level via and method of selective formation of a barrier layer for a contact level via
05/24/2001US20010001498 Field effect transistors, integrated circuitry, methods of forming field effect transistor gates, and methods of forming integrated circuitry
05/24/2001US20010001496 Semiconductor devices
05/24/2001US20010001428 Circuit board and semiconductor device, and method of manufacturing the same
05/24/2001US20010001427 Electrical interconnect structure and method of forming electrical interconnects having electromigration-inhibiting segments
05/24/2001US20010001416 Heat sink and method for making the same
05/24/2001US20010001406 Embossing a channel or opening into the green tape of the desired size under heat and pressure, screen printing an ink of conductive material to fill embossed channel or openings, firing the green tape
05/23/2001EP1102525A1 Printed wiring board and method for producing the same
05/23/2001EP1102316A1 Multichip IC card with bus structure
05/23/2001EP1102315A2 A method to avoid copper contamination on the sidewall of a via or a dual damascene structure
05/23/2001EP1102182A2 Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by the method, and recording medium storing the program
05/23/2001EP1101837A1 Moisture corrosion inhibitor layer for Al-alloy metallization layers, particularly for electronic devices and corresponding manufacturing method
05/23/2001EP1101834A2 Method of depositing materials on substrates
05/23/2001EP1101250A1 Lead frame attachment for optoelectronic device
05/23/2001EP1101248A2 Substrate for high-voltage modules
05/23/2001DE19955277A1 Method to influence thermal economy of body, e.g. electronic equipment
05/23/2001DE19954895A1 Anordnung zur elektrischen Verbindung zwischen Chips in einer dreidimensional ausgeführten Schaltung Arrangement for electrical connection between circuit chips in a three-dimensionally performed
05/23/2001DE19954888A1 Verpackung für einen Halbleiterchip Package for a semiconductor chip
05/23/2001DE10026067A1 Düsen-Lotzufuhrgerät und Lötverfahren Nozzle Lotzufuhrgerät and soldering
05/23/2001DE10000759C1 Production of justifying marks in a structure with integrated circuits comprises applying a first planar metal layer over a semiconductor substrate, applying an insulating layer, inserting metal and depositing a second metal layer
05/23/2001CN2431643Y Radiating device combination
05/23/2001CN2431642Y Radiating device combination
05/23/2001CN1296642A RF circuit module
05/23/2001CN1296641A 显示装置 Display device
05/23/2001CN1296640A Anisotropic conductor film, semiconductor chip, and method of packaging
05/23/2001CN1296638A Semiconductor device with transparent link area for silicide applications and fabrication thereof
05/23/2001CN1296289A Semiconductor device
05/23/2001CN1296088A Steel wire spring clamp head, wire-guiding frame conveying belt and electroplating system
05/22/2001US6236612 Integrated semiconductor memory configuration with self-buffering of supply voltages
05/22/2001US6236569 Attaching heat sinks to integrated circuits
05/22/2001US6236568 Heat-dissipating structure for integrated circuit package
05/22/2001US6236567 Electronic device package with enhanced heat dissipation effect
05/22/2001US6236566 Cooling element for a power electronic device and power electronic device comprising same
05/22/2001US6236565 Chip stack with active cooling system
05/22/2001US6236297 Combinational inductor
05/22/2001US6236228 Structure and method of repair of integrated circuits
05/22/2001US6236129 Motor with hydrodynamic bearing and heat sink device employing this motor
05/22/2001US6236116 Semiconductor device having a built-in heat sink and process of manufacturing same
05/22/2001US6236115 High density integrated circuit packaging with chip stacking and via interconnections
05/22/2001US6236114 Bonding pad structure
05/22/2001US6236112 Semiconductor device, connecting substrate therefor, and process of manufacturing connecting substrate
05/22/2001US6236111 Hybrid circuit substrate mountable micro-electromechanical component
05/22/2001US6236110 Power semiconductor module
05/22/2001US6236109 Multi-chip chip scale package
05/22/2001US6236108 Substrate for holding a chip of semi-conductor package, semi-conductor package, and fabrication process of semi-conductor package
05/22/2001US6236107 Encapsulate resin LOC package and method of fabrication
05/22/2001US6236106 Wiring structure with divided wiring conductors to achieve planarity in an overlying SOG layer
05/22/2001US6236105 Semiconductor device with improved planarity achieved through interlayer films with varying ozone concentrations
05/22/2001US6236103 Integrated high-performance decoupling capacitor and heat sink
05/22/2001US6236101 Metallization outside protective overcoat for improved capacitors and inductors
05/22/2001US6236098 Heat spreader
05/22/2001US6236092 Mixed mode device
05/22/2001US6236091 Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide
05/22/2001US6236090 Semiconductor device and method for reducing contact resistance between an electrode and a semiconductor substrate
05/22/2001US6236061 Semiconductor crystallization on composite polymer substrates
05/22/2001US6235997 LSI package with equal length transmission Lines
05/22/2001US6235996 Interconnection structure and process module assembly and rework
05/22/2001US6235648 Semiconductor device including insulation film and fabrication method thereof