Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
06/2001
06/19/2001US6248960 Ceramics substrate with electronic circuit and its manufacturing method
06/19/2001US6248959 Substrate with die area having same CTE as IC
06/19/2001US6248951 Dielectric decal for a substrate of an integrated circuit package
06/19/2001US6248664 Forming active layer and oxide layer on backing for semiconductors
06/19/2001US6248661 Method for monitoring bubble formation and abnormal via defects in a spin-on-glass planarization, etchback process
06/19/2001US6248659 Method for forming an interconnect structure
06/19/2001US6248657 Semiconductor device and method for manufacturing the same
06/19/2001US6248647 Fabrication of integrated circuits on both sides of a semiconductor wafer
06/19/2001US6248615 Wiring patterned film and production thereof
06/19/2001US6248614 Flip-chip package with optimized encapsulant adhesion and method
06/19/2001US6248613 Process for fabricating a crack resistant resin encapsulated semiconductor chip package
06/19/2001US6248612 Method for making a substrate for an integrated circuit package
06/19/2001US6248611 LOC semiconductor assembled with room temperature adhesive
06/19/2001US6248454 Composition for semiconductor encapsulation, which comprises epoxy resin, phenolic resin, cure accelerator, cure accelerator-containing microcapsules having core/shell structure with accelerator encapsulated in thermoplastic resin
06/19/2001US6248429 Metallized recess in a substrate
06/19/2001US6248206 Apparatus for sidewall profile control during an etch process
06/19/2001US6247228 Electrical connection with inwardly deformable contacts
06/19/2001US6247221 Method for sealing and/or joining an end of a ceramic filter
06/14/2001WO2001043519A1 Cooler for electronic devices
06/14/2001WO2001043518A1 Chip package with molded underfill
06/14/2001WO2001043201A1 Semiconductor device with a diode, and method of manufacturing such a device
06/14/2001WO2001043194A1 Intelligent gate-level fill methods for reducing global pattern density effects
06/14/2001WO2001043193A2 Dual-die integrated circuit package
06/14/2001WO2001043192A1 A method and an arrangement relating to electronic circuitry
06/14/2001WO2001043191A1 Semiconductor device comprising a security coating and smartcard provided with such a device
06/14/2001WO2001043190A1 Interposer device
06/14/2001WO2001043189A2 Integrated electronic circuit with at least one inductor and method for producing such a circuit
06/14/2001WO2001043188A1 Electronic part module, method of producing the same, etc.
06/14/2001WO2001043181A1 Methods for producing packaged integrated circuit devices & packaged integrated circuit devices produced thereby
06/14/2001WO2001043169A2 Methods for separating microcircuit dies from wafers
06/14/2001WO2001042742A1 Integrated sound transmitter and receiver, and corresponding method for making same
06/14/2001WO2001042529A1 METHOD FOR FORMING TiSiN FILM, DIFFUSION PREVENTIVE FILM COMPRISING TiSiN FILM, SEMICONDUCTOR DEVICE AND ITS PRODUCTION METHOD, AND APPARATUS FOR FORMING TiSiN FILM
06/14/2001WO2001042360A1 Flame-retardant epoxy resin composition and laminate made with the same
06/14/2001WO2001042359A1 Flame retardant phosphorus element-containing epoxy resin compositions
06/14/2001US20010003771 Cured polyepoxides or epoxidized novolaks containing 9,10-dihydro-9-oxa-10-phosphaphenanthrene-10-oxide group; high elastic modulus, and decomposition temperature, use in printed circuit and semiconductor encapsulant applications
06/14/2001US20010003752 Crystalline form of 4- [ 5-methyl-3-phenylisoxazol-4-yl ] benzenesulfonamide
06/14/2001US20010003675 Method for manufacturing a semiconductor device
06/14/2001US20010003658 Leaving the photoresist layer on the gate electrode after patterning it, then heating to reflow the photoresist to cover the side edges of the gate electrode; three-layer thin film is used as source, drain and pixel electrodes
06/14/2001US20010003656 Electronic device assembly and a method of connecting electronic devices constituting the same
06/14/2001US20010003502 Means for dissipating heat in electrical apparatus
06/14/2001US20010003382 Semiconductor device comprising layered positional detection marks and manufacturing method therof
06/14/2001US20010003380 Method and an arrangement relating to electronic circuitry
06/14/2001US20010003379 Semiconductor device and method of fabricating the same
06/14/2001US20010003377 Heat sink for a semiconductor device
06/14/2001US20010003376 Integrated circuit package architecture with improved electrostatic discharge protection
06/14/2001US20010003375 Dual-die integrated circuit package
06/14/2001US20010003374 Semiconductor device comprising a security coating and smartcard provided with such a device
06/14/2001US20010003373 Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications
06/14/2001US20010003372 Semiconductor package structure having universal lead frame and heat sink
06/14/2001US20010003371 Unit type clip lead terminal, clip lead terminal connecting method, lead terminal connecting board, and method of producing board with lead terminals
06/14/2001US20010003306 Torsion bar clamp apparatus and method for inproving thermal and mechanical contact between stacked electronic components
06/14/2001US20010003304 Heat sink with textured regions
06/14/2001US20010003303 Heat sink with cross channel fluid communication
06/14/2001US20010003302 Narrow channel heat sink with tapered fins
06/14/2001US20010003300 Non-contact radiating structure and radiating method
06/14/2001US20010003296 Forming a projecting electrode by applying and hardening a thermosetting conductive adhesive on first connecting electrode, applying a hardenable conductive adhesive on projecting electrode, aligning components, hardening
06/14/2001CA2394458A1 Methods for producing packaged integrated circuit devices & packaged integrated circuit devices produced thereby
06/14/2001CA2392975A1 Dual-die integrated circuit package
06/13/2001EP1107657A2 Means for dissipating heat in electrical apparatus
06/13/2001EP1107655A2 Low profile interconnect structure
06/13/2001EP1107654A1 Sheet for printed wiring board, method of forming via, resin sheet having filled via, printed wiring board and method of manufacturing the same
06/13/2001EP1107313A2 On-chip test circuit to control the succession of exposure masks
06/13/2001EP1107312A2 Multiple line grids incorporating therein circuit elements
06/13/2001EP1107311A2 Semiconductor die package including cup-shaped leadframe
06/13/2001EP1107310A2 Isolation improvement of high power semiconductor modules
06/13/2001EP1107308A1 Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer
06/13/2001EP1107307A1 Semiconductor package, semiconductor device, electronic device, and method of manufacturing semiconductor package
06/13/2001EP1107306A1 Semiconductor package, semiconductor device, electronic device and production method for semiconductor package
06/13/2001EP1107305A2 Method for mounting a semiconductor device
06/13/2001EP1107302A2 Method and apparatus for reducing fixed charges in a semiconductor device
06/13/2001EP1107299A2 Process for producing semiconductor devices
06/13/2001EP1107298A2 Solution containing metal component, method of and apparatus for forming thin metal film
06/13/2001EP1106040A1 Method for producing interconnections with electrically conductive cross connections between the top and the bottom part of a substrate and interconnections having such cross connections
06/13/2001EP1105922A1 Combination positive temperature coefficient resistor and metal-oxide semiconductor field-effect transistor devices
06/13/2001EP1105921A1 Process for mapping metal contaminant concentration on a silicon wafer surface
06/13/2001EP1105838A1 Support element for an integrated circuit module
06/13/2001EP1105545A1 Preparation of metal-matrix composite materials with high particulate loadings by concentration
06/13/2001EP1105191A1 Safety unit
06/13/2001EP0908076B1 Grid array assembly and method of making
06/13/2001DE19954941A1 Verfahren zum Integrieren eines Chips innerhalb einer Leiterplatte A method of integrating a chip within a printed circuit board
06/13/2001DE10059688A1 Substrat für das Packaging eines elektronischen Bauelements und piezoelektrisches Resonanzbauelement unter Verwendung desselben Of the same substrate for packaging an electronic component and a piezoelectric resonance device using
06/13/2001DE10049556A1 Integrated microelectronic module has hydrogen getter element of titanium with external surface essentially free of oxygen and devices for fixing it to one of inner surfaces in housing
06/13/2001DE10019838A1 Laminate capacitor for high frequency circuit has penetration conduction bodies with array pitch set to 0.085mm or less
06/13/2001CN1299581A Method of making microwave, multifunction modules using fluoropolymer substrates
06/13/2001CN1299520A Wire bond attachment of a integrated circuit package to a heat sink
06/13/2001CN1299518A Semiconductor pakage and flip-chiop bonding method therefor
06/13/2001CN1299231A Heat radiator with fastener for heat-generating electronic elements
06/13/2001CN1299230A Low side surface internet structure
06/13/2001CN1067202C Image display apparatus with line number conversion and method therefor
06/12/2001US6246584 Heat sink
06/12/2001US6246583 Method and apparatus for removing heat from a semiconductor device
06/12/2001US6246581 Heated PCB interconnect for cooled IC chip modules
06/12/2001US6246247 Probe card assembly and kit, and methods of using same
06/12/2001US6246243 Semi-fusible link system
06/12/2001US6246124 Encapsulated chip module and method of making same
06/12/2001US6246123 Molding material made from triglycidyl isocyanurate, alkali zinc borosilicate glass filler and hexahydrophthalic anhydride curing agent used in optical components for transmitting/receiving optical data signals
06/12/2001US6246122 Electrostatic discharge protective schemes for integrated circuit packages
06/12/2001US6246121 High performance flip-chip semiconductor device
06/12/2001US6246119 Structure of a dual damascene
06/12/2001US6246118 Low dielectric semiconductor device with rigid, conductively lined interconnection system