Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
05/2001
05/31/2001US20010002051 Semiconductor device
05/31/2001US20010001989 Microelectronic connections with liquid conductive elements
05/31/2001US20010001983 Localized thermo manager for semiconductor devices
05/31/2001US20010001981 Heat pipe type cooler
05/31/2001US20010001976 Apparatus and method for fabricating buried and flat metal features
05/31/2001US20010001954 Forming a titanium/titanium nitride film on a semiconductor substrate surface by vapor deposition where the substrate support has a protective silicon nitride coating to prevent contamination the support material; no current leakage
05/31/2001US20010001898 Heat sink and method for making the same
05/31/2001DE19957302A1 Substrate used in the production of integrated circuits comprises a first insulating layer on the substrate, a second insulating layer on the first insulating layer, hollow chambers
05/31/2001DE19956903A1 Process for the integration of PIN diodes comprises depositing a diode structure on a substrate, structuring a mesa structure, producing a metal bump, bonding a heat sink to the bump
05/31/2001DE19956565A1 Manufacturing heat sink for electrical components involves structuring metallisation on at least one of two or more substrates with metallisation and channel openings on ceramic layer
05/31/2001DE19955537A1 Verfahren zur Herstellung eines Trägerelements für einen IC-Baustein A process for producing a carrier element for an IC module
05/31/2001DE19952768A1 Vorrichtung zum thermischen Verbinden eines elektronischen Bauelementes mit einem Kühlkörper Apparatus for thermally bonding an electronic component to a heat sink
05/31/2001DE19950580A1 Überspannungsschutzanordnung Overvoltage protection order
05/31/2001DE10058446A1 Semiconducting device with radiation structure has connecting components between first and second radiating components and chip with better conductivity than tungsten and molybdenum
05/31/2001DE10056832A1 Semiconductor module has printed circuit board with opening aligned with heat dissipation surface of substrate, which is fastened directly on the heat sink using screw
05/31/2001DE10043172A1 Halbleiter-Baustein und Verfahren zur Herstellung desselben Of the same semiconductor device and methods for making
05/31/2001DE10020590A1 Mehrfachmass-Streifen und Verfahren zum Ausgleich desselben The same multiple mass strip and method of compensation
05/30/2001EP1104226A1 Production method for flexible substrate
05/30/2001EP1104225A1 Surface mounting component and mounted structure of surface mounting component
05/30/2001EP1104026A2 Ground plane for a semiconductor chip
05/30/2001EP1104025A1 Semiconductor device
05/30/2001EP1104024A2 Semiconductor package and method for forming semiconductor package
05/30/2001EP1104017A2 Method of flip-chip mounting a semiconductor chip to a circuit board
05/30/2001EP1104016A1 Lead assembly for semiconductor devices and assembling method therefor
05/30/2001EP1104015A2 Heat sink and method of fabricating same
05/30/2001EP1103995A1 Electronic component, and electronic apparatus in which the electronic component is mounted and its manufacturing method
05/30/2001EP1103858A2 Photolithographic method to make a fuse in integrated circuit with localised blowing point
05/30/2001EP1103639A2 Plating apparatus and method
05/30/2001EP1103634A1 Method for contact plated copper deposition
05/30/2001EP1103633A1 Method for copper plating deposition
05/30/2001EP1103168A2 High density printed circuit substrate and method of fabrication
05/30/2001EP1103072A1 Thin-layered semiconductor structure comprising a heat distribution layer
05/30/2001EP0826165B1 Alignment device and lithographic apparatus provided with such a device
05/30/2001CN2432683Y Radiator fan
05/30/2001CN2432629Y Fastener joining device
05/30/2001CN1297584A Method of mfg. semiconductor device, semiconductor device, narrow pitch connector, electrostatic actuator, ink jet head, ink-jet printer, micromachine, liquid crystal panel, and electronic device
05/30/2001CN1297567A Conductive paste, ceramic multilayer substrate, and method for mfg. ceramic multilayer substrate
05/30/2001CN1297255A Mixed fuse technique
05/30/2001CN1297253A Wiring baseboard, semiconductor device with wiring baseboard, and mfg. and installing method thereof
05/30/2001CN1066577C Heat-pipe type cooling apparatus
05/30/2001CN1066575C Method and apparatus for transversely access of frame of IC guided line
05/30/2001CN1066574C Method for mfg. encapsulated substrate type semiconductor device
05/30/2001CN1066494C Process for producing metal-bonded-ceramic material
05/29/2001US6240199 Electronic apparatus having improved scratch and mechanical resistance
05/29/2001US6239987 Case for semiconductor circuit of a surge protector
05/29/2001US6239983 Circuit board, manufacturing method therefor, and bump-type contact head and semiconductor component packaging module using the circuit board
05/29/2001US6239980 Multimodule interconnect structure and process
05/29/2001US6239974 Electrical assembly that includes a heat sink which is attached to a substrate by a clip
05/29/2001US6239972 Integrated convection and conduction heat sink for multiple mounting positions
05/29/2001US6239703 Communication pad structure for semiconductor devices
05/29/2001US6239669 High frequency package
05/29/2001US6239615 High-performance interconnect
05/29/2001US6239591 Method and apparatus for monitoring SOI hysterises effects
05/29/2001US6239499 Consistent alignment mark profiles on semiconductor wafers using PVD shadowing
05/29/2001US6239497 Substrate for packing semiconductor device and method for packing a semiconductor device in the substrate
05/29/2001US6239496 Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same
05/29/2001US6239495 Multichip semiconductor device and memory card
05/29/2001US6239494 Wire bonding CU interconnects
05/29/2001US6239491 Integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level, and process for making same
05/29/2001US6239489 Reinforcement of lead bonding in microelectronics packages
05/29/2001US6239488 Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate
05/29/2001US6239487 Lead frame with heat spreader and semiconductor package therewith
05/29/2001US6239486 Semiconductor device having cap
05/29/2001US6239485 Reduced cross-talk noise high density signal interposer with power and ground wrap
05/29/2001US6239484 Underfill of chip-under-chip semiconductor modules
05/29/2001US6239483 Semiconductor device
05/29/2001US6239482 Integrated circuit package including window frame
05/29/2001US6239480 Modified lead frame for improved parallelism of a die to package
05/29/2001US6239479 Thermal neutron shielded integrated circuits
05/29/2001US6239461 Semiconductor device capacitor having a recessed contact plug
05/29/2001US6239402 Polycrystalline structure of incorporatesd aluminum nitride crystals and magnesium oxide to improve corrosion resistance against halogen-based corrosive gases; heat-insulating
05/29/2001US6239384 Microelectric lead structures with plural conductors
05/29/2001US6239383 Ball-grid array IC packaging frame
05/29/2001US6239382 Device and method of controlling the bowing of a soldered or adhesively bonded assembly
05/29/2001US6239381 Circuit board for a semiconductor device and method of making the same
05/29/2001US6239380 Singulation methods and substrates for use with same
05/29/2001US6239367 Multi-chip chip scale package
05/29/2001US6239366 Face-to-face multi-chip package
05/29/2001US6239042 Process for realizing an intermediate dielectric layer for enhancing the planarity in semiconductor electronic devices
05/29/2001US6239031 Stepper alignment mark structure for maintaining alignment integrity
05/29/2001US6239029 Sacrificial germanium layer for formation of a contact
05/29/2001US6239026 Nitride etch stop for poisoned unlanded vias
05/29/2001US6239025 High aspect ratio contact structure for use in integrated circuits
05/29/2001US6239024 Method of filling gap with dielectrics
05/29/2001US6239023 Method to reduce the damages of copper lines
05/29/2001US6239021 Dual barrier and conductor deposition in a dual damascene process for semiconductors
05/29/2001US6239019 Interconnect structure using a combination of hard dielectric and polymer as interlayer dielectrics
05/29/2001US6239016 Multilevel interconnection in a semiconductor device and method for forming the same
05/29/2001US6238977 Method for fabricating a nonvolatile memory including implanting the source region, forming the first spacers, implanting the drain regions, forming the second spacers, and forming a source line on the source and second spacers
05/29/2001US6238970 Method for fabricating a DRAM cell capacitor including etching upper conductive layer with etching byproduct forming an etch barrier on the conductive pattern
05/29/2001US6238955 Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry
05/29/2001US6238954 COF packaged semiconductor
05/29/2001US6238953 Lead frame, resin-encapsulated semiconductor device and fabrication process for the device
05/29/2001US6238952 Low-pin-count chip package and manufacturing method thereof
05/29/2001US6238951 Process for producing a sealing and mechanical strength ring between a substrate and a chip hybridized by bumps on the substrate
05/29/2001US6238950 Integrated circuit with tightly coupled passive components
05/29/2001US6238949 Method and apparatus for forming a plastic chip on chip package module
05/29/2001US6238948 Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material
05/29/2001US6238938 Methods of making microelectronic connections with liquid conductive elements
05/29/2001US6238533 Integrated PVD system for aluminum hole filling using ionized metal adhesion layer