Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
06/2001
06/12/2001US6246117 Semiconductor device comprised of a ball grid array and an insulating film with preformed land openings
06/12/2001US6246116 Buried wiring line
06/12/2001US6246115 Semiconductor package having a heat sink with an exposed surface
06/12/2001US6246114 Semiconductor device and resin film
06/12/2001US6246113 Integrated circuit package architecture with improved electrostatic discharge protection
06/12/2001US6246112 Interleaved signal trace routing
06/12/2001US6246111 Universal lead frame type of quad flat non-lead package of semiconductor
06/12/2001US6246110 Downset lead frame for semiconductor packages
06/12/2001US6246109 Semiconductor device and method for fabricating the same
06/12/2001US6246108 Integrated circuit package including lead frame with electrically isolated alignment feature
06/12/2001US6246107 Semiconductor device arrangement having configuration via adjacent bond pad coding
06/12/2001US6246106 Lead frame
06/12/2001US6246105 Semiconductor device and manufacturing process thereof
06/12/2001US6246102 Integrated circuits, transistors, data processing systems, printed wiring boards, digital computers, smart power devices, and processes of manufacture
06/12/2001US6246085 Semiconductor device having a through-hole of a two-level structure
06/12/2001US6246075 Test structures for monitoring gate oxide defect densities and the plasma antenna effect
06/12/2001US6246073 Semiconductor device and method for producing the same
06/12/2001US6246016 Edge-mountable integrated circuit package and method of attaching the same to a printed wiring board
06/12/2001US6246015 Printed circuit board for ball grid array semiconductor packages
06/12/2001US6246010 High density electronic package
06/12/2001US6245996 Electrical interconnect structure having electromigration-inhibiting segments
06/12/2001US6245692 Method to selectively heat semiconductor wafers
06/12/2001US6245673 Method of forming tungsten silicide film
06/12/2001US6245672 Forming a metal film on doped region of a semiconductor body surface, carbiding or oxycarbiding the metal film surface by introducing carbon and/or oxygen and heat treating to densify, overcoating with copper metallization
06/12/2001US6245671 Semiconductor processing method of forming an electrically conductive contact plug
06/12/2001US6245665 Semiconductor device and method of fabricating the same
06/12/2001US6245664 Method and system of interconnecting conductive elements in an integrated circuit
06/12/2001US6245663 IC interconnect structures and methods for making same
06/12/2001US6245661 Vapor deposition in the contact hole of a dielectric film on a semiconductor substrate a copper-aluminum layer, vapor depositing an electroconductive film of another metal onto dielectric and overcoating with a layer of the first alloy
06/12/2001US6245659 Semiconductor device and method for manufacturing the same
06/12/2001US6245658 Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system
06/12/2001US6245651 Method of simultaneously forming a line interconnect and a borderless contact to diffusion
06/12/2001US6245646 Film frame substrate fixture
06/12/2001US6245622 Doping active region of integrated circuit surface at an oblique angle to form amorphous structure, coating with metal film and heat treating to form metal silicide
06/12/2001US6245611 Process for manufacturing semiconductor integrated circuit device
06/12/2001US6245600 Method and structure for SOI wafers to avoid electrostatic discharge
06/12/2001US6245599 Circuit wiring system circuit wiring method semi-conductor package and semi-conductor package substrate
06/12/2001US6245598 Method for wire bonding a chip to a substrate with recessed bond pads and devices formed
06/12/2001US6245597 Method for reducing die cracking in integrated circuits
06/12/2001US6245596 Method of producing semiconductor device with heat dissipation metal layer and metal projections
06/12/2001US6245595 Techniques for wafer level molding of underfill encapsulant
06/12/2001US6245587 Method for making semiconductor devices having backside probing capability
06/12/2001US6245584 Method for detecting adjustment error in photolithographic stepping printer
06/12/2001US6245490 Method of manufacturing a circuit board having metal bumps and a semiconductor device package comprising the same
06/12/2001US6245448 Base metal layer with reduction potentials, isolation layer and second reduction potential for multilayer element
06/12/2001US6245442 Aluminum-silicon carbide composite
06/12/2001US6245380 Multilayer; dielectrics, barriers, glue, metal; polishing
06/12/2001US6245259 Wavelength-converting casting composition and light-emitting semiconductor component
06/12/2001US6245186 Electronic package with compressible heatsink structure
06/12/2001US6245171 Multi-thickness, multi-layer green sheet lamination and method thereof
06/12/2001US6244332 Heat sink
06/12/2001US6244331 Heatsink with integrated blower for improved heat transfer
06/12/2001US6244056 Controlled production of ammonia and other gases
06/12/2001US6243945 Method for manufacturing electronic parts
06/12/2001US6243944 Residue-free method of assembling and disassembling a pressed joint with low thermal resistance
06/12/2001CA2221502C Semiconductor package
06/07/2001WO2001041521A1 Thermally conductive electronic device case
06/07/2001WO2001041520A1 U-shaped heat sink assembly
06/07/2001WO2001041218A1 Method for recycled separated wafer and recycled separated wafer
06/07/2001WO2001041213A1 Heat conductive sheet and method of producing the sheet
06/07/2001WO2001041212A2 Integrated circuit package
06/07/2001WO2001041207A1 Packaging of integrated circuits and vertical integration
06/07/2001WO2001041203A1 Improved flourine doped sio2 film
06/07/2001WO2001040354A1 Poly(phenylene ether) - polyvinyl thermosetting resin
06/07/2001US20010003068 Coating substrate surface with coating solution containing as film-forming solute uniformly dissolved in an organic solvent a nitrogen-containing organic compound to form coating layer, drying coating layer by evaporating, baking
06/07/2001US20010003064 Forming interconnect made of copper overlying a substrate, conducting pretreatment of the copper at 300 degrees C or less, forming dielectric film on copper by chemical vapor deposition
06/07/2001US20010003060 Multilevel interconnecting structure in semiconductor device and method of forming the same
06/07/2001US20010003059 Ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer; portable telephones
06/07/2001US20010003055 Fixing semiconductor chips respectively to carrier areas, semiconductor chips being fixed on thin portions of insulating board, covering semiconductor chips with resin layer, and separating resin layer and board into segments
06/07/2001US20010003054 Providing first and second chip regions on silicon wafer, wherein first resist pattern for semiconductor device is to be formed in first chip region, and second chip region includes a plurality of evaluation regions, determining data rate
06/07/2001US20010003053 Area of multilayer wiring substrate can be reduced, and cracks caused by residual stress produced by a firing step can be prevented
06/07/2001US20010003051 Having logic circuit connected to external terminals, built-in memory connected to logic circuit, and burn-in test circuit for, when performing burn-in test, writing predetermined data into said built-in memory
06/07/2001US20010003049 Method and mold for manufacturing semiconductor device, semiconductor device, and method for mounting the device
06/07/2001US20010003048 Semiconductor device and manufacturing method thereof
06/07/2001US20010003033 Method and apparatus for reducing non-uniformity area effects in the manufacture of semiconductor devices
06/07/2001US20010003015 Of titanium, by adding a flow of hydrogen and nitrogen to the reaction chamber; processor readable medium containing a program that causes the reactor chamber to passivate the titanium layer
06/07/2001US20010002874 Ic card module, manufacturing method therefor, hybrid integrated circuit module, and manufacturing method thereof
06/07/2001US20010002807 Substrate for packaging electronic component and piezoelectric resonance component using the same
06/07/2001US20010002795 Test chip for molding material including filler and method for evaluating the molding material
06/07/2001US20010002734 Selectively coating bond pads
06/07/2001US20010002733 Semiconductor device and method of manufacturing same
06/07/2001US20010002732 Substrate with at least two metal structures disposed thereon, and method for fabricating it
06/07/2001US20010002730 Semiconductor device and manufacturing method thereof
06/07/2001US20010002729 Integrated circuit heat sink support and retention mechanism
06/07/2001US20010002727 Semiconductor device and module of the same
06/07/2001US20010002726 Semiconductor device and method for making the same
06/07/2001US20010002724 Semiconductor device and manufacturing method thereof
06/07/2001US20010002723 Motor driving device
06/07/2001US20010002722 Methods of forming integrated circuit capacitors having electrodes therein that comprise conductive plugs
06/07/2001US20010002721 Electrically blowable fuse with reduced cross-sectional area
06/07/2001US20010002713 Semiconductor device
06/07/2001US20010002624 Tip structures.
06/07/2001US20010002541 Spray cooling system
06/07/2001DE19957089A1 Chip carrier or lead-frame with carrier plate comprising at least two spatially- and electrically-isolated part-pieces, has part-pieces of carrier plate retained by frame-parts made of electrically-insulated material
06/07/2001DE19940560A1 Verfahren zur Herstellung eines Halbleiterchips mit nach dem Siliziumprozess einstellbarer elektrischer Eigenschaft A process for producing a semiconductor chip with silicon after the process adjustable electrical property
06/07/2001DE10042269A1 Semiconductor package for DIMM (dual in-line memory module), has length larger than body width and smaller than total package width
06/07/2001DE10041623A1 Multi-layered ceramic substrate manufacture involves preparing raw compound multilayer body with metallic foils, and baking it while restraining contraction of green sheets in direction of main surface
06/07/2001DE10014303C1 Secure semiconductor device with protection against hacking e.g. for chip card
06/06/2001EP1104934A2 Method to selectively heat semiconductor wafers
06/06/2001EP1104647A1 Method for manufacturing solderless high density electronic modules