Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
10/2001
10/23/2001US6307213 Method for making a fuse structure for improved repaired yields on semiconductor memory devices
10/23/2001US6307162 Integrated circuit wiring
10/23/2001US6307161 Partially-overcoated elongate contact structures
10/23/2001US6307160 High-strength solder interconnect for copper/electroless nickel/immersion gold metallization solder pad and method
10/23/2001US6307159 Bump structure and method for making the same
10/23/2001US6306792 Mixing with water, subjecting to pressure cooking, measuring electroconductivity of extraction mixture
10/23/2001US6306765 Method for the formation of thin films for use as a semiconductor device
10/23/2001US6306762 Forming aluminum alloy, forming metal layer in direct contact with aluminum alloy, forming metal nitride; conductively coupled so conduction continues even if alloy layer becomes non-conducting
10/23/2001US6306757 Method for forming a multilevel interconnect
10/23/2001US6306755 Method for endpoint detection during dry etch of submicron features in a semiconductor device
10/23/2001US6306754 Method for forming wiring with extremely low parasitic capacitance
10/23/2001US6306753 Feasible, gas-dielectric interconnect process
10/23/2001US6306752 Connection component and method of making same
10/23/2001US6306751 Apparatus and method for improving ball joints in semiconductor packages
10/23/2001US6306750 Bonding pad structure to prevent inter-metal dielectric cracking and to improve bondability
10/23/2001US6306749 Bond pad with pad edge strengthening structure
10/23/2001US6306746 Backend process for fuse link opening
10/23/2001US6306745 Chip-area-efficient pattern and method of hierarchal power routing
10/23/2001US6306744 Filter capacitor construction
10/23/2001US6306731 Semiconductor device and method for fabricating the same
10/23/2001US6306728 Stable high voltage semiconductor device structure
10/23/2001US6306714 Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide
10/23/2001US6306688 Method of reworkably removing a fluorinated polymer encapsulant
10/23/2001US6306687 Tape under frame for conventional-type IC package assembly
10/23/2001US6306686 Method of fabricating an electronic package with interconnected chips
10/23/2001US6306685 Method of molding a bump chip carrier and structure made thereby
10/23/2001US6306684 Stress reducing lead-frame for plastic encapsulation
10/23/2001US6306682 Method of fabricating a ball grid array integrated circuit package having an encapsulating body
10/23/2001US6306680 Power overlay chip scale packages for discrete power devices
10/23/2001US6306528 Method for the controlling of certain second phases in aluminum nitride
10/23/2001US6306526 Lid suitable for use in hermetic sealing of semiconductor package, comprising metal plate having solder layer secured thereto by cladding prior to formation of hermetic seal
10/23/2001US6306511 Substrate comprising compact of first powder comprising partially sintered glass, functional layer comprising compact of second powder comprising ceramic material having specified electrical property, diffusion bonded by substrate material
10/23/2001US6306495 Film for use in microelectronic devices and methods of producing same
10/23/2001US6305464 Method for producing a cooling element, and a cooling element
10/23/2001US6305095 Methods and circuits for mask-alignment detection
10/23/2001CA2067784C Method and device for hermetic encapsulation of electronic components
10/18/2001WO2001078478A1 Cooling device for cooling components of the power electronics, said device comprising a micro heat exchanger
10/18/2001WO2001078475A1 Method and device for fabricating electrical connecting elements, and connecting element
10/18/2001WO2001078472A1 Flexible circuit with plated cover layer and overlapping protective layer
10/18/2001WO2001078147A1 Lead frame design for reduced wire sweep
10/18/2001WO2001078146A2 Bonding pad in semiconductor device
10/18/2001WO2001078145A2 Boding pad in semiconductor device
10/18/2001WO2001078144A1 Vertical structure and process for semiconductor wafer-level chip scale packages
10/18/2001WO2001078143A1 Removable heat transfer apparatus for a pin grid array (pga) dev ice
10/18/2001WO2001078141A2 USE OF AlN AS COPPER PASSIVATION LAYER AND THERMAL CONDUCTOR
10/18/2001WO2001078140A2 Chip carrier, relative manufacturing process, and electronic component incorporating such a carrier
10/18/2001WO2001078139A1 Common electrode wire for plating
10/18/2001WO2001078138A1 Flip chip semiconductor device including a compliant support for supporting a heat sink
10/18/2001WO2001078137A1 Semiconductor photodetector
10/18/2001WO2001078120A1 Method of forming vias in silicon carbide and resulting devices and circuits
10/18/2001WO2001078109A2 High rigidity, multi-layered, semiconductor package and method of making the same
10/18/2001WO2001078093A2 Distributed capacitor
10/18/2001WO2001078041A1 Component provided with a description
10/18/2001WO2001077192A1 Aromatic oligomer, phenolic resin composition containing the same, and epoxy resin composition and cured object obtained therefrom
10/18/2001WO2001076855A1 Thermally conductive sheet
10/18/2001WO2001015508A9 Integrated emi shield utilizing a hybrid edge
10/18/2001US20010031925 Apparatus and method for collecting data useful for determining the parameters of an alert window for timing delivery or etc signals to a heart under varying cardiac conditons
10/18/2001US20010031851 Thermosetting resin composition
10/18/2001US20010031828 Film-type adhesive for electronic components, and electronic components bonded therewith
10/18/2001US20010031690 Insulator ceramic is composed of an magnesium oxide-magnesium aluminate (MgO-MgAl2O4) ceramic powder, and a glass powder containing oxides of silicon, boron and with or without alumina, also contains oxides of 1a, 11a, zinc and copper
10/18/2001US20010031563 Semiconductor device and method of fabricating the same
10/18/2001US20010031555 Method for forming aluminum interconnection
10/18/2001US20010031553 Leads under chip in conventional IC package
10/18/2001US20010031549 Magnetic layer processing
10/18/2001US20010031548 Method for forming chip scale package
10/18/2001US20010031545 Bonding layer method in a semiconductor device
10/18/2001US20010031516 Pedestal fuse
10/18/2001US20010031514 Method and apparatus for fabricating self-assembling microstructures
10/18/2001US20010031513 Semiconducator device and a method of manufacturing the same
10/18/2001US20010031511 Stress-free silicon wafer and a die or chip made therefrom and method
10/18/2001US20010031508 Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects
10/18/2001US20010031506 Etch bias distribution across semiconductor wafer
10/18/2001US20010031345 Laminated radiation member, power semiconductor apparatus, and method for producing the same
10/18/2001US20010030853 Heat sink assembly for dissipating heat of an electronic package mounted on an electrical socket
10/18/2001US20010030852 Heat sink apparatus and method of attaching the heat sink apparatus to a device
10/18/2001US20010030591 Integrated inductor
10/18/2001US20010030552 Conductive material for integrated circuit fabrication
10/18/2001US20010030493 Laminated ceramic electronic device
10/18/2001US20010030371 High density flip chip memory arrays
10/18/2001US20010030370 Microelectronic assembly having encapsulated wire bonding leads
10/18/2001US20010030369 Methods and apparatus for forming a film on s substrate
10/18/2001US20010030368 Semiconductor device and fabrication method
10/18/2001US20010030367 Semiconductor integrated circuit device and fabrication method for semiconductor integrated circuit device
10/18/2001US20010030366 Semiconducting system and production method
10/18/2001US20010030365 Damascene wiring structure and semiconductor device with damascene wirings
10/18/2001US20010030363 Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
10/18/2001US20010030361 Circuit and method for providing interconnections among individual integrated circuit chips in a multi-chip module
10/18/2001US20010030359 Housing for semiconductor chips
10/18/2001US20010030358 Semiconductor device package
10/18/2001US20010030357 Semiconductor apparatus substrate, semiconductor apparatus, and method of manufacturing thereof and electronic apparatus
10/18/2001US20010030356 Transverse hybrid LOC package
10/18/2001US20010030355 Saw-singulated leadless plastic chip carrier
10/18/2001US20010030344 Semiconductor device and method for manufacturing the same
10/18/2001US20010030334 Wiring for semiconductor device and method for forming the same
10/18/2001US20010030330 High speed semiconductor photodetector and method of fabricating same
10/18/2001US20010030185 Connection of a junction to an electrical conductor track on a plate
10/18/2001US20010030062 Conductive composition
10/18/2001US20010030061 Surface-mounting substrate and structure comprising substrate and part mounted on the substrate
10/18/2001US20010030060 Electronic component protection devices and methods
10/18/2001US20010030059 Circuit component built-in module, radio device having the same, and method for producing the same