| Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155) |
|---|
| 01/01/2002 | US6335560 Semiconductor device having a mark section and a dummy pattern |
| 01/01/2002 | US6335548 Semiconductor radiation emitter package |
| 01/01/2002 | US6335494 Multiple power distribution for delta-I noise reduction |
| 01/01/2002 | US6335493 Multilayer wiring board |
| 01/01/2002 | US6335492 Tape carrier package with improved connecting terminals and a method of electrically interconnecting the tape carrier package to external circuitry |
| 01/01/2002 | US6335491 Interposer for semiconductor package assembly |
| 01/01/2002 | US6335417 Modified polyimide resin and thermosetting resin composition containing the same |
| 01/01/2002 | US6335297 Forming insulating layer on semiconductor substrate, sequentially forming semiconductor layer and tungsten film on insulating layer, nitrifying tungsten film with heat treatment, selectively etching tungsten film and semiconductor |
| 01/01/2002 | US6335289 Manufacturing method of semiconductor device |
| 01/01/2002 | US6335279 Method of forming contact holes of semiconductor device |
| 01/01/2002 | US6335273 Surface treatment of low-K SiOF to prevent metal interaction |
| 01/01/2002 | US6335271 Method of forming semiconductor device bump electrodes |
| 01/01/2002 | US6335265 Forming a catalyst layer on a bottom of first separation groove in front surface of semiconductor substrate, forming a first metal layer selectively in first separation groove by electroless plating |
| 01/01/2002 | US6335250 Semiconductor device and method for the manufacture thereof |
| 01/01/2002 | US6335229 Inductive fuse for semiconductor device |
| 01/01/2002 | US6335228 Method for making an anti-fuse |
| 01/01/2002 | US6335227 Method of fabricating a lead-on-chip (LOC) semiconductor device |
| 01/01/2002 | US6335225 High density direct connect LOC assembly |
| 01/01/2002 | US6335224 Protection of microelectronic devices during packaging |
| 01/01/2002 | US6335223 Method for producing a resin-sealed semiconductor device |
| 01/01/2002 | US6335107 Useful as an electrical connector |
| 01/01/2002 | US6335104 Providing a copper pad surface; selectively depositing a protection layer of phosphorus or boron-containing metal alloy on the copper pad surface; depositing adhesion layer of noble metal |
| 01/01/2002 | US6335077 For filling a via-hole formed in a green ceramic sheet |
| 01/01/2002 | US6335050 Method of manufacturing a ferrite magnetic film structure having magnetic anisotropy |
| 01/01/2002 | US6334915 Sheet which consists essentially of copper, nickel, silicon, magnesium, and at least one of manganese and chromium; having specified average grain size and size of intermetallic compound precipitate of nickel and silicon |
| 01/01/2002 | US6334750 Fastener for a heat-radiator on a chip |
| 01/01/2002 | US6334567 Component and method for production thereof |
| 01/01/2002 | US6334481 Retainer for a cooling device |
| 01/01/2002 | US6334480 Cooling device with micro cooling fin |
| 01/01/2002 | US6334247 High density integrated circuit apparatus, test probe and methods of use thereof |
| 01/01/2002 | CA2228486C Cooling structure for multi-chip module |
| 12/28/2001 | CA2350057A1 Planarized plastic modules for integrated circuits |
| 12/27/2001 | WO2001099194A2 Semiconductor arrangement |
| 12/27/2001 | WO2001099193A1 Semiconductor chip and semiconductor device using the semiconductor chip |
| 12/27/2001 | WO2001099189A1 Method and apparatus for edge connection between elements of an integrated circuit |
| 12/27/2001 | WO2001099188A2 Semiconductor package and method |
| 12/27/2001 | WO2001099184A2 Dual damascene process utilizing a low-k dual dielectric |
| 12/27/2001 | WO2001099172A1 Electrical insulation of chip wafers by liquid phase sio2 deposition |
| 12/27/2001 | WO2001099168A1 Semiconductor device and method of manufacture thereof |
| 12/27/2001 | WO2001099166A1 Thin film forming method |
| 12/27/2001 | WO2001099148A2 Electrical fuses employing reverse biasing to enhance programming |
| 12/27/2001 | WO2001098793A2 Systems for testing integraged circuits during burn-in |
| 12/27/2001 | WO2001098724A1 Graphite-based heat sink |
| 12/27/2001 | WO2001098398A1 Flame-retarded polyamides |
| 12/27/2001 | WO2001098016A2 Laser system for processing target material |
| 12/27/2001 | WO2001080304A8 Improved test structures and methods for inspecting and utilizing the same |
| 12/27/2001 | WO2001069159A8 High performance heat exchange assembly |
| 12/27/2001 | WO2001037338A3 Method for integrating a chip in a printed board and integrated circuit |
| 12/27/2001 | WO2001001469A3 Process for designing a mask |
| 12/27/2001 | US20010056162 Comprising a maleimide compound or polymer modified by a maleimide compound, free-radical catalyst and photoinitiator; single chip packaging; reworking |
| 12/27/2001 | US20010055891 High density semiconductors |
| 12/27/2001 | US20010055873 Semiconductor device and fabrication method thereof |
| 12/27/2001 | US20010055872 Semiconductor device having multilayer wiring structure and method for manufacturing the same |
| 12/27/2001 | US20010055868 Apparatus and method for metal layer streched conducting plugs |
| 12/27/2001 | US20010055866 Lead structure and method of manufacture |
| 12/27/2001 | US20010055856 Method of dicing a wafer from the back side surface thereof |
| 12/27/2001 | US20010055850 Method of forming a capacitor and an electrical connection thereto, and method of forming DRAM circuitry |
| 12/27/2001 | US20010055848 Fuse area structure having guard ring surrounding fuse opening in semiconductor device and method of forming the same |
| 12/27/2001 | US20010055839 Method of fabricating a dielectric antifuse structure |
| 12/27/2001 | US20010055837 Method of attaching a leadframe to singulated semiconductor dice |
| 12/27/2001 | US20010055834 Method of making semiconductor packages at wafer level |
| 12/27/2001 | US20010055825 Laser marking techniques |
| 12/27/2001 | US20010055819 Method of manufacturing a semiconductor device comprising a semiconductor body having a surface provided with a coil having magnetic core |
| 12/27/2001 | US20010055714 Electronic power device |
| 12/27/2001 | US20010055703 Method for the controlling of certain second phases in aluminum nitride |
| 12/27/2001 | US20010055605 Printed circuits; containing cockroach repellent |
| 12/27/2001 | US20010055230 Semiconductor memory and memory board therewith |
| 12/27/2001 | US20010055203 Package substrate |
| 12/27/2001 | US20010055201 Circuit configuration having at least one nanoelectronic component and method for fabricating the component |
| 12/27/2001 | US20010055199 Heat sink |
| 12/27/2001 | US20010055198 Heat sink |
| 12/27/2001 | US20010054905 Probe card assembly and kit |
| 12/27/2001 | US20010054771 Method for making projected contact structures for engaging bumped semiconductor devices |
| 12/27/2001 | US20010054769 Protective layers prior to alternating layer deposition |
| 12/27/2001 | US20010054768 Bonding pad structure of a semiconductor device and method of fabricating the same |
| 12/27/2001 | US20010054766 Process for making a planar integrated circuit interconnect |
| 12/27/2001 | US20010054765 Semiconductor device and method and apparatus for manufacturing the same |
| 12/27/2001 | US20010054764 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same |
| 12/27/2001 | US20010054762 Semiconductor device and method of fabricating the same |
| 12/27/2001 | US20010054761 Dual-dies packaging structure and packaging method |
| 12/27/2001 | US20010054760 Semiconductor integrated circuit |
| 12/27/2001 | US20010054759 Semiconductor device |
| 12/27/2001 | US20010054757 Multi-layer wiring board substrate and semiconductor device using the multi-layer wiring substrate |
| 12/27/2001 | US20010054756 Multi-layered semiconductor device and method for producing the same |
| 12/27/2001 | US20010054754 Surface-mounting type electronic circuit unit suitable for miniaturization and easy to manufacture |
| 12/27/2001 | US20010054753 Semiconductor package and mount board, and mounting method using the same |
| 12/27/2001 | US20010054752 High current capacity semiconductor device package and lead frame with large area connection posts and modified outline |
| 12/27/2001 | US20010054751 Semiconductor device and liquid crystal module |
| 12/27/2001 | US20010054750 Semiconductor leadframes plated with lead-free solder and minimum palladium |
| 12/27/2001 | US20010054745 Metal fuse in copper dual damascene |
| 12/27/2001 | US20010054739 Vertical component peripheral structure |
| 12/27/2001 | US20010054731 Semiconductor device having a lower electrode aperture that is larger than the photolithography resolution of the capacitor pattern |
| 12/27/2001 | US20010054721 Semiconductor integrated circuit and semiconductor integrated circuit wiring layout method |
| 12/27/2001 | US20010054710 System and method for inspecting semiconductor device |
| 12/27/2001 | US20010054709 Chemically synthesized and assembled electronic devices |
| 12/27/2001 | US20010054640 Wire bonding apparatus for connecting semiconductor devices |
| 12/27/2001 | US20010054600 Method and apparatus for simulating standard test wafers |
| 12/27/2001 | US20010054513 Package substrate |
| 12/27/2001 | US20010054481 Method for making multilayer board having a cavity |
| 12/27/2001 | US20010054390 Wafer support system |