Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
05/2002
05/14/2002US6388321 Anisotropic conductive film and resin filling gap between a flip-chip and circuit board
05/14/2002US6388320 Vertically integrated semiconductor configuration
05/14/2002US6388319 Three commonly housed diverse semiconductor dice
05/14/2002US6388318 Surface mount-type package of ball grid array with multi-chip mounting
05/14/2002US6388317 Solid-state chip cooling by use of microchannel coolant flow
05/14/2002US6388316 Semiconductor module
05/14/2002US6388315 Tap connections for circuits with leakage suppression capability
05/14/2002US6388314 Single deposition layer metal dynamic random access memory
05/14/2002US6388313 Multi-chip module
05/14/2002US6388312 Repairable multi-chip package
05/14/2002US6388311 Semiconductor device
05/14/2002US6388310 Semiconductor device with a passivation film
05/14/2002US6388305 Electrically programmable antifuses and methods for forming the same
05/14/2002US6388277 Auto placement and routing device and semiconductor integrated circuit
05/14/2002US6388273 Substrate material for mounting a semiconductor device, substrate for mounting a semiconductor device, semiconductor device, and method of producing the same
05/14/2002US6388272 A sic semiconductor device in which the third conductive layer comprises one of an os layer and a tac/wc/w layer.
05/14/2002US6388269 Metal interconnection structure for evaluation on electromigration
05/14/2002US6388264 Optocoupler package being hermetically sealed
05/14/2002US6388207 Electronic assembly with trench structures and methods of manufacture
05/14/2002US6388206 Microcircuit shielded, controlled impedance “Gatling gun”via
05/14/2002US6388203 Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
05/14/2002US6388200 Electronic interconnection medium having offset electrical mesh plane
05/14/2002US6388199 Selectively adjusting surface tension of soldermask material
05/14/2002US6388198 Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality
05/14/2002US6387824 Method for forming porous forming film wiring structure
05/14/2002US6387821 Forming, on a semiconductor substrate wiring made of cupper or its alloy; forming insulating film on wiring; forming via hole by dry etching; removing contaminanats by using cleaning solution containing complexing agent; forming a barrier metal
05/14/2002US6387806 Filling an interconnect opening with different types of alloys to enhance interconnect reliability
05/14/2002US6387805 Copper alloy seed layer for copper metallization
05/14/2002US6387803 Method for forming a silicide region on a silicon body
05/14/2002US6387797 Method for reducing the capacitance between interconnects by forming voids in dielectric material
05/14/2002US6387796 Semiconductor device and method of manufacturing the same
05/14/2002US6387795 Wafer-level packaging
05/14/2002US6387794 Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device
05/14/2002US6387793 Metallization; applying solder bumps; heating
05/14/2002US6387792 Method of fabricating a dielectric antifuse structure
05/14/2002US6387747 Method to fabricate RF inductors with minimum area
05/14/2002US6387742 Thermal conductivity enhanced semiconductor structures and fabrication processes
05/14/2002US6387738 Leaving the photoresist layer on the gate electrode after patterning it, then heating to reflow the photoresist to cover the side edges of the gate electrode; three-layer thin film is used as source, drain and pixel electrodes
05/14/2002US6387736 Method and structure for bonding layers in a semiconductor device
05/14/2002US6387734 Semiconductor package, semiconductor device, electronic device and production method for semiconductor package
05/14/2002US6387732 Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip and packages formed thereby
05/14/2002US6387731 Method and apparatus for reducing BGA warpage caused by encapsulation
05/14/2002US6387730 Hybrid S.C. devices and method of manufacture thereof
05/14/2002US6387729 Method for adhering and sealing a silicon chip in an integrated circuit package
05/14/2002US6387728 Method for fabricating a stacked chip package
05/14/2002US6387726 Passivation, patterning, forming polyimide, etching
05/14/2002US6387714 Die-to-insert permanent connection and method of forming
05/14/2002US6387537 Epoxy resin composition and semiconductor device
05/14/2002US6387536 Aluminum alloy thin film for semiconductor device electrode with excellent corrosion resistance, hillock resistance, void resistance and low electrical resistivity, comprising as alloy components yttrium and hafnium in specified amounts
05/14/2002US6387507 Microelectronic package comprising high temperature co-fired ceramic body mated to low temperature co-fired ceramic body by bonding layer comprising electrically nonconductive portion and plurality of electrically conductive portions
05/14/2002US6387387 Electronic component material containing pest repellent, electronic component using the same, and its manufacturing method
05/14/2002US6387205 Coating multilayer thermosetting resin on cloth fibers; curing
05/14/2002US6387190 Multistages; removal polishing particles, then purification
05/14/2002US6386785 Engaging post for a heat-dissipating device
05/14/2002US6386456 Memory card identification system
05/14/2002US6386278 Cooler
05/14/2002US6386275 Surrounding type fin-retaining structure of heat radiator
05/14/2002US6386274 Heat sink assembly
05/14/2002US6386191 CSP plate holder
05/14/2002CA2361311A1 A semiconductor photodiode and an optical receiver
05/14/2002CA2071496C Direct thermocompression bonding for thin electronic power chips
05/10/2002WO2002037917A1 Parts cooling apparatus for electric/electronic equipments
05/10/2002WO2002037914A1 Arrangement for cooling a component generating heat energy using cooling fluid
05/10/2002WO2002037911A1 Method and arrangement relating to providing a substrate with cavities
05/10/2002WO2002037565A2 Method of connecting conductors on different levels of a microelectronic device and associated apparatus
05/10/2002WO2002037564A2 Film material comprising metal spikes and method for the production thereof
05/10/2002WO2002037563A2 A leadframe and semiconductor package
05/10/2002WO2002037562A1 Lead frame and semiconductor device using this
05/10/2002WO2002037558A1 Semiconductor device and its manufacturing method
05/10/2002WO2002037557A2 Method for producing an integrated circuit, at least partially transforming an oxide layer into a conductive layer
05/10/2002WO2002037553A1 Integrated circuit connection by conductive deposition through a perforated film
05/10/2002WO2002015269A3 Wiring through terminal via fuse window
05/10/2002WO2002013270A3 Semiconductor component and a method for identifying a semiconductor component
05/10/2002WO2002009176A3 Method for applying adjusting marks on a semiconductor disk
05/10/2002WO2001082377A3 Circuit
05/10/2002WO2001075983A3 Multilayer capacitor structure having an array of concentric ring-shaped plates for deep sub-micron cmos
05/10/2002WO2001067512A3 Method and apparatus for delivering power to high performance electronic assemblies
05/09/2002US20020056070 Method and apparatus for extracting parasitic element of semiconductor circuit
05/09/2002US20020055284 Socket apparatus for removably mounting electronic packages
05/09/2002US20020055282 Electronic components with plurality of contoured microelectronic spring contacts
05/09/2002US20020055277 Chip carrier for a high-frequency electronic package
05/09/2002US20020055265 Method of forming vias in silicon carbide and resulting devices and circuits
05/09/2002US20020055256 Reducing copper line resistivity by smoothing trench and via sidewalls
05/09/2002US20020055251 Local interconnect structure for integrated circuit devices, source structure for the same, and method for fabricating the same
05/09/2002US20020055250 Dielectric structure and method for minimizing erosion during chemical mechanical polishing of metals
05/09/2002US20020055249 Method of manufacturing an integrated semiconductor device having a plurality of connection levels
05/09/2002US20020055248 Method for forming a top interconnection level and bonding pads on an integrated circuit chip
05/09/2002US20020055246 Method and apparatus for reducing substrate bias voltage drop
05/09/2002US20020055244 Method of forming a substrate contact in a field effect transistor formed over a buried insulator layer
05/09/2002US20020055214 Stacked local interconnect structure and method of fabricating same
05/09/2002US20020055206 Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor
05/09/2002US20020055203 Semiconductor device and method of manufacturing the same
05/09/2002US20020054955 Coating uninsulated portion of copper circuit with layer of ceramic having thickness for soldering without fluxing; integrated circuits
05/09/2002US20020054658 Method and apparatus for high speed signaling
05/09/2002US20020054514 Semiconductor memory device and defect remedying method thereof
05/09/2002US20020054484 Electrical device allowing for increased device densities
05/09/2002US20020054482 Electrical apparatus
05/09/2002US20020054471 Method of making a parallel capacitor laminate
05/09/2002US20020054467 Multi-layered substrate with a built-in capacitor design and a method of making the same
05/09/2002US20020054004 Control signal part and liquid crystal display including the control signal