Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
05/2002
05/23/2002US20020060358 Package of an image sensor device
05/23/2002US20020060357 Quad flat non-leaded package structure for housing CMOS sensor
05/23/2002US20020060356 Power semiconductor device
05/23/2002US20020060354 Semiconductor device and method for fabricating the same
05/23/2002US20020060352 Semiconductor integrated circuit
05/23/2002US20020060350 Thinfilm Fuse/ Antifuse Device and Use of Same in Printhead
05/23/2002US20020060342 Semiconductor device with chamfered substrate and method of making the same
05/23/2002US20020060323 Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof
05/23/2002US20020060318 Routable high-density interfaces for integrated circuit devices
05/23/2002US20020060160 Method and structure for producing bumps on an IC package substrate
05/23/2002US20020060091 Ceramic circuit board and method of manufacturing the same
05/23/2002US20020060085 Conductive cap, electronic component, and method of forming insulating film of conductive cap
05/23/2002US20020060084 Flip-chip package with underfill dam that controls stress at chip edges
05/23/2002US20020060064 Heat sink assembly
05/23/2002US20020059723 Electronic package for electronic components and method of making same
05/23/2002US20020059722 Method of mounting a semiconductor device to a substrate and a mounted structure
05/23/2002US20020059721 Apparatus and method for printed circuit board repair
05/23/2002DE10153666A1 High density contact arrangement for integrated circuit chips has diagonal layout to reduce separation
05/23/2002DE10152589A1 Radiator plate for power module, has dispersant having smaller thermal expansion coefficient, that is dispersed more on heat receiving surface than that on heat radiating surface
05/23/2002DE10115248A1 Wire bonding method for wafer level chip scale package, involves forming metal bump directly on metal pad which is provided on wafer surface, without forming under bump metallurgy layer
05/23/2002DE10065895C1 Electronic component used as an integrated circuit comprises a screen for electromagnetic scattering, a semiconductor chip made from a semiconductor substrate and an electrically conducting trenched layer
05/23/2002DE10058886C1 Production of an integrated semiconductor product used as ferroelectric random access memories comprises forming semiconductor wafer, molding connections, exposing the connections, applying protective layer and polishing
05/23/2002DE10057973A1 Device for a clocked semiconductor chip has both cooling element and ferrite emitted radiation shield bound to the chip
05/23/2002DE10057635A1 Method for processing a substrate comprises applying a photolacquer layer to the substrate and structuring so that some regions of the substrate are covered with the photolacquer
05/23/2002DE10057435C1 Leakage current regulation circuit for FET's compares sum leakage current through parallel test FET's with required leakage current for bias voltage adjustment
05/23/2002DE10056411C1 Abgleichelement für integrierte Halbleiterschaltungen Adjustment element for a semiconductor integrated circuit
05/23/2002DE10056387A1 Cooling device for electronic component and production method has cooling fins fixed permanently on one side of the baseplate groove only
05/23/2002DE10056297A1 Integrated semiconductor memory has connection pads which can support different functions in different stages of production
05/23/2002DE10056281A1 Electronic component comprises a semiconductor chip having an active upper side with integrated circuits and a passive rear side without integrated circuits
05/23/2002DE10055454A1 Cooling body for electronic components or devices having a heat emitting region formed by an open pore metal foam body
05/23/2002DE10055177A1 Electronic component has separating walls between connecting leads
05/22/2002EP1207727A2 Compliant laminate connector
05/22/2002EP1207563A2 Direct bonding of flip-chip light-emitting diode and flip-chip ESD protection chip to electrodes in a package
05/22/2002EP1207555A1 Flip-chip on film assembly for ball grid array packages
05/22/2002EP1207554A1 Electronic part
05/22/2002EP1207553A1 Fixing device for pressure contacted high power semiconductor device
05/22/2002EP1207426A1 Method for aligning a semiconductor wafer
05/22/2002EP1206825A1 Universal energy conditioning interposer with circuit architecture
05/22/2002EP1206800A1 Microbeam assembly and associated method for integrated circuit interconnection to substrates
05/22/2002EP1206799A1 Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
05/22/2002EP1206325A2 Vapor phase connection techniques
05/22/2002CN2493000Y Pull fastening radiating fin fixture
05/22/2002CN2492944Y Chip molding and packing apparatus
05/22/2002CN1350703A Robust interconnect structure
05/22/2002CN1350701A Method for handling thinned chips for introducing them into chip cards
05/22/2002CN1350700A Process for mapping metal contaminant concentration on a silicon wafer surface
05/22/2002CN1350330A Radiator and method for manufacturing the same and extrusion clamp
05/22/2002CN1350329A Semiconductor devices and their method of production, and mounting method thereof
05/22/2002CN1350325A Contact structure member and production method thereof, and probe contact assembly using said contact structure member
05/22/2002CN1350323A Lead wire frame and method for manufacturing lead wire frame
05/22/2002CN1350218A Fastener
05/22/2002CN1350201A Wiring base plate, display device, semiconductor chip and electronic machine
05/22/2002CN1350045A Binder and electric apparatus
05/22/2002CN1350032A Epoxy resin composition and method of producing the same
05/22/2002CN1350031A Fire-retardant resin composition, preliminary-dip piece, laminated board, metal cladded laminated board, printed circuit-board and multi-layer printed circuit board
05/22/2002CN1350026A Phenol curing agent for epoxy resin and epoxy resin composition using said curing agent
05/22/2002CN1085413C Semiconductor device and making method
05/22/2002CN1085410C Integrated circuit with gate-array interconnections rounted over memory area
05/22/2002CN1085409C Bottom-lead semiconductor or package
05/22/2002CN1085408C Semiconductor package and cead frame
05/22/2002CN1085406C 半导体器件 Semiconductor devices
05/21/2002USRE37707 Leadframe with heat dissipator connected to S-shaped fingers
05/21/2002US6393603 Circuit design method calculating antenna size of conductive member connected to gate oxide film of transistor with approximate expression
05/21/2002US6392898 Package substrate
05/21/2002US6392889 Fastener for heat sink
05/21/2002US6392888 Heat dissipation assembly and method of assembling the same
05/21/2002US6392887 PLGA-BGA socket using elastomer connectors
05/21/2002US6392886 Heat sink assembly
05/21/2002US6392530 Resistor array board
05/21/2002US6392468 Electrically programmable fuse
05/21/2002US6392429 Temporary semiconductor package having dense array external contacts
05/21/2002US6392428 Wafer level interposer
05/21/2002US6392309 Semiconductor device including solid state imaging device
05/21/2002US6392308 Semiconductor device having bumper portions integral with a heat sink
05/21/2002US6392307 Semiconductor device
05/21/2002US6392306 Semiconductor chip assembly with anisotropic conductive adhesive connections
05/21/2002US6392305 Chip scale package of semiconductor
05/21/2002US6392304 Multi-chip memory apparatus and associated method
05/21/2002US6392301 Chip package and method
05/21/2002US6392300 Semiconductor device having an alignment mark formed on the uppermost layer of a multilayer wire
05/21/2002US6392299 Integrated circuit and associated fabrication process
05/21/2002US6392298 Functional lid for RF power package
05/21/2002US6392295 Semiconductor device
05/21/2002US6392294 Semiconductor device with stable protection coating
05/21/2002US6392293 Semiconductor package with sloped outer leads
05/21/2002US6392292 Multi-level stacked semiconductor bear chips with the same electrode pad patterns
05/21/2002US6392291 Semiconductor component having selected terminal contacts with multiple electrical paths
05/21/2002US6392290 Vertical structure for semiconductor wafer-level chip scale packages
05/21/2002US6392289 Integrated circuit substrate having through hole markings to indicate defective/non-defective status of same
05/21/2002US6392288 Lead frame for assembly for thin small outline plastic encapsulated packages
05/21/2002US6392287 Semiconductor package and fabricating method thereof
05/21/2002US6392286 Semiconductor chip packaging system and a semiconductor chip packaging method using the same
05/21/2002US6392259 Semiconductor chip with surface covering
05/21/2002US6392252 Semiconductor device
05/21/2002US6392251 Test structures for identifying open contacts and methods of making the same
05/21/2002US6392164 Multi-level circuit substrate, method for manufacturing same and method for adjusting a characteristic impedance therefor
05/21/2002US6392163 Controlled-shaped solder reservoirs for increasing the volume of solder bumps
05/21/2002US6392158 Structure equipped with electric contacts formed through said structure substrate and method for obtaining said structure
05/21/2002US6392145 Semiconductor device including and integrated circuit housed in an array package having signal terminals arranged about centrally located power supply terminals
05/21/2002US6392144 Micromechanical die attachment surcharge