Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
07/2002
07/09/2002US6417533 Semiconductor device having capacitor which assures sufficient capacity without requiring large space and method of producing the same
07/09/2002US6417463 Depopulation of a ball grid array to allow via placement
07/09/2002US6417116 Semiconductor device having a multilayer interconnection structure
07/09/2002US6417097 Methods of forming a contact structure in a semiconductor device
07/09/2002US6417089 Method of forming solder bumps with reduced undercutting of under bump metallurgy (UBM)
07/09/2002US6417088 Method of application of displacement reaction to form a conductive cap layer for flip-chip, COB, and micro metal bonding
07/09/2002US6417087 Forming a bond pad opening having a barrier layer film on the bottom surface of the upper portion of the opening, and forming vias which extend downwardly through the bottom surface
07/09/2002US6417076 Automated combi deposition apparatus and method
07/09/2002US6417068 Semiconductor device navigation using laser scribing
07/09/2002US6417039 Method of manufacturing a semiconductor device comprising a semiconductor body having a surface provided with a coil having a magnetic core
07/09/2002US6417029 Compliant package with conductive elastomeric posts
07/09/2002US6417027 High density stackable and flexible substrate-based devices and systems and methods of fabricating
07/09/2002US6417026 Bump electrodes are connected to the electrode pattern while in contact with the edge portions of the electrically insulating layer and the protection layer; high density mounting; surface acoustic wave device
07/09/2002US6417025 Integrated circuit packages assembled utilizing fluidic self-assembly
07/09/2002US6417018 Asymmetrical molding method for multiple part matrixes
07/09/2002US6417017 Optosemiconductor device and the method for its manufacture
07/09/2002US6416851 Bearing for refrigerating machine compressor and compressor
07/09/2002US6416849 Method and structure to reduce low force pin pull failures in ceramic substrates
07/09/2002US6416831 Evacuated package and a method of producing the same
07/09/2002US6416812 Electroless plating bath using source of cupric ions, reducing agent and complexing agent in basic solution
07/09/2002US6415977 Method and apparatus for marking and identifying a defective die site
07/09/2002US6415853 Wind cover locking element structure of heat radiator
07/09/2002US6415852 Heat sink assembly
07/09/2002US6415627 Sorber having a cooling mechanism
07/09/2002US6415626 Sorber having flexible housing
07/09/2002US6415619 Multi-load refrigeration system with multiple parallel evaporators
07/09/2002US6415612 Method and apparatus for external cooling an electronic component of a mobile hardware product, particularly a notebook computer, at a docking station having a thermoelectric cooler
07/04/2002WO2002052912A1 Heat sink
07/04/2002WO2002052647A2 Semiconductor device comprising an arrangement of an electrically programmable non-volatile memory element
07/04/2002WO2002052646A1 Integrated circuit device
07/04/2002WO2002052645A2 Enhanced die-up ball grid array packages and method for making the same
07/04/2002WO2002052644A2 Thermally enhanced microcircuit package and method of forming same
07/04/2002WO2002052643A2 Semiconductor wafer manufacturing process
07/04/2002WO2002052642A2 Method for eliminating reaction between photoresist and organosilicate glass
07/04/2002WO2002052641A2 Contact and via structure and method of fabrication
07/04/2002WO2002052640A1 Method of reducing the specific resistance of an electrically conducting molybdenum layer
07/04/2002WO2002052633A2 Assembly for mounting an integrated circuit on a support
07/04/2002WO2002052630A2 Structural reinforcement of highly porous low k dielectric films by ild posts
07/04/2002WO2002052589A1 Semiconductor device, and method and apparatus for manufacturing semiconductor device
07/04/2002WO2002052588A1 Semiconductor device, and method and apparatus for manufacturing semiconductor device
07/04/2002WO2002035289A3 Method and materials for printing particle-enhanced electrical contacts
07/04/2002WO2002032636A3 Method for making micromolds
07/04/2002WO2002023592A3 Method and apparatus for reducing ic die mass and thickness while improving strength characteristics
07/04/2002WO2002015245A3 Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence
07/04/2002WO2002013258A3 Backside contact for integrated circuit and method of forming same
07/04/2002WO2001073864A3 Thin-film battery having ultra-thin electrolyte and associated method
07/04/2002WO2000070676A9 High-density electronic package, and method for making same
07/04/2002US20020087941 Semiconductor device having embedded array
07/04/2002US20020086801 Dry thermal interface material
07/04/2002US20020086585 Insulation device of an electric element
07/04/2002US20020086561 Wiring board
07/04/2002US20020086549 Resist mask having measurement marks for measuring the accuracy of overlay of a photomask disposed on semiconductor wafer
07/04/2002US20020086542 Fabrication of semiconductor devices
07/04/2002US20020086533 Forming copper bonding pad on top level of metallization; chemical mechanical polishing of bonding pad; etching pad; depositing a barrier layer over bonding pad; depositing aluminum or aluminum-copper alloy over barreier layer
07/04/2002US20020086520 Semiconductor device having bump electrode
07/04/2002US20020086519 Stacked vias and method
07/04/2002US20020086518 Methods for producing electrode and semiconductor device
07/04/2002US20020086516 Sub-minimum wiring structure
07/04/2002US20020086513 Mask repattern process
07/04/2002US20020086500 Semiconductor package and fabricating method thereof
07/04/2002US20020086487 Integrated circuit fabrication method for self-aligned copper diffusion barrier
07/04/2002US20020086486 Method of manufacturing semiconductor device and the semiconductor device
07/04/2002US20020086475 Zero overlap contact/via with metal plug
07/04/2002US20020086466 Integrated circuit with conductive lines disposed within isolation regions
07/04/2002US20020086462 Method and structure to reduce the damage associated with programming electrical fuses
07/04/2002US20020086453 Method of fabricating a liquid crystal display with reduced contact resistance
07/04/2002US20020086451 Manufacture method for semiconductor inspection apparatus
07/04/2002US20020086429 Method for determination of cure and oxidation of spin-on dielectric polymers
07/04/2002US20020086111 Chemisorbing monolayers of a hydrazine-based compound and one or more refractory metal compounds on a substrate to form refractory metal nitride layer
07/04/2002US20020086109 Chemical vapor deposition wherein at least one kind of organic substance including benzene nucleuses is used as a benzene nucleus source so that insulator includes benzene nucleuses
07/04/2002US20020085761 Enhanced uniqueness for pattern recognition
07/04/2002US20020085746 Semiconductor wafer on which recognition marks are formed and method for sawing the wafer using the recognition marks
07/04/2002US20020085364 Electronic package with high density interconnect layer
07/04/2002US20020085362 Low cost feature to indicate package orientation
07/04/2002US20020085357 Heat sink assembly retainer device
07/04/2002US20020085356 Electronic device
07/04/2002US20020085336 High performance via capacitor and method for manufacturing same
07/04/2002US20020084868 High-frequency switching module and high-frequency apparatus equipped with the same
07/04/2002US20020084824 Stacked voltage rails for low-voltage DC distribution
07/04/2002US20020084538 Apparatus and method for reducing interposer compression during molding process
07/04/2002US20020084537 System and method for packaging a semiconductor die
07/04/2002US20020084535 Chip scale package
07/04/2002US20020084534 Semiconductor package including flip chip
07/04/2002US20020084533 Efficient multiple power and ground distribution of SMT IC packages
07/04/2002US20020084532 IC package pressure release apparatus and method
07/04/2002US20020084530 Conductive lines with reduced pitch
07/04/2002US20020084529 Interconnect structures and a method of electroless introduction of interconnect structures
07/04/2002US20020084528 Wafer level package and method for manufacturing the same
07/04/2002US20020084527 Hardening of copper to improve copper CMP performance
07/04/2002US20020084526 Semiconductor device and manufacturing method thereof
07/04/2002US20020084524 Ball grid array package comprising a heat sink
07/04/2002US20020084523 Resin sealed semiconductor device
07/04/2002US20020084522 Semiconductor device using interposer substrate and manufacturing method therefor
07/04/2002US20020084521 Flip-chip on film assembly for ball grid array packages
07/04/2002US20020084519 Semiconductor chip stack package and fabrication method thereof
07/04/2002US20020084518 Semiconductor device
07/04/2002US20020084517 Assembly with connecting structure
07/04/2002US20020084516 Individualized low parasitic power distribution lines deposited over active integrated circuits
07/04/2002US20020084515 Known good die using existing process infrastructure
07/04/2002US20020084514 Wiring substrate for high frequency applications