Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
07/2002
07/18/2002US20020092166 Heat pipe and method and apparatus for making same
07/18/2002US20020092159 Multi-layer interconnect
07/18/2002DE10151928A1 Current rectifier has internal noise filter and sealed radiation substrate and fins
07/18/2002DE10147365A1 Halbleitervorrichtung, Verfahren für ihre Herstellung und Verfahren für ihren Entwurf Semiconductor device, method for their preparation, and methods for their design
07/18/2002DE10065857A1 Heat dissipation arrangement for plastic housings for electronic units has increased thermal conductivity area(s) produced during multiple component injection molding or by molding insert
07/18/2002DE10065495A1 Leistungshalbleitermodul The power semiconductor module
07/17/2002EP1223791A2 Organic luminescence device
07/17/2002EP1223620A2 Electrostatic discharge protection structure
07/17/2002EP1223613A2 Electrode structure for semiconductor device, manufacturing method and apparatus for the same
07/17/2002EP1223612A1 Semiconductor device mounting circuit board, method of producing the same, and method of producing mounting structure using the same
07/17/2002EP1222725A1 Universal multi-functional common conductive shield structure for electrical circuitry and energy conditioning
07/17/2002EP1222664A2 Method for identifying an integrated circuit
07/17/2002EP0963459B1 Wafer support apparatus
07/17/2002EP0847594B1 Method of assembling an adhesively bonded electronic device using a deformable substrate
07/17/2002EP0770267B1 Method of manufacturing a device, by which method a substrate with semiconductor element and conductor tracks is glued to a support body with metallization
07/17/2002CN2501282Y Finned radiator
07/17/2002CN2501188Y Heat exchanger of liquid-vapour phase latent heat
07/17/2002CN2501187Y 散热器 Heat sink
07/17/2002CN2501186Y Improved structure of fastener for CPU radiator
07/17/2002CN2501100Y Radiator for CPU
07/17/2002CN1359608A Symmetrical package for semiconductor die
07/17/2002CN1359539A Semiconductor device, method of manufacturing the same, and structure for mounting semiconductor device
07/17/2002CN1359538A Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer
07/17/2002CN1359537A Electronic part
07/17/2002CN1359535A Method and device for interconnect radio frequency power sic filed effect transistors
07/17/2002CN1359476A Optomodule
07/17/2002CN1359161A Non-rectangular thermoelectric miniature assembly and cooling device for chip using said assembly
07/17/2002CN1359159A Packaged video image sensitive chip with light permeable piece and package method
07/17/2002CN1359157A Semiconductor device with capacitance component and making method
07/17/2002CN1359155A Semiconductor device and making method
07/17/2002CN1359154A Semiconductor device
07/17/2002CN1359153A packaged video image sensitive chip and peackaging method
07/17/2002CN1359152A Water cooling method and apparatus for heat conductive isolation sheet type rectification device
07/17/2002CN1359151A Ultrathin package device with high heat radiation and making method
07/17/2002CN1359150A Ball pin array package substrate and making method
07/17/2002CN1359149A Packaged IC substrate and making method
07/17/2002CN1359147A Convex formation method, semiconductor device and making method and semiconductor chip
07/17/2002CN1359137A Super heat-conductive pipe lamp
07/17/2002CN1359020A LCD device
07/17/2002CN1358813A Conductive adhesion agent, assembling structure and method for making said assembling structure
07/17/2002CN1358798A High-temp. under mould-filling material with low heat generating in use
07/17/2002CN1087871C Capacitor similar component in IC
07/16/2002US6421819 Integrated circuit layout designing system and power source eliminating method to be employed in the same using arranging power blocks
07/16/2002US6421816 Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system
07/16/2002US6421456 Semiconductor wafer on which recognition marks are formed and method for sawing the wafer using the recognition marks
07/16/2002US6421254 Multi-chip module having interconnect dies
07/16/2002US6421248 Chip card module
07/16/2002US6421244 Power module
07/16/2002US6421242 Heat sink clip with pressing cam
07/16/2002US6421241 Heat exchanging chassis
07/16/2002US6421239 Integral heat dissipating device
07/16/2002US6420943 Conducting path with two different end characteristic impedances determined by doping
07/16/2002US6420792 Semiconductor wafer edge marking
07/16/2002US6420791 Alignment mark design
07/16/2002US6420790 Semiconductor device
07/16/2002US6420789 Ball grid array chip packages having improved testing and stacking characteristics
07/16/2002US6420788 Method for mounting a semiconductor chip on a substrate and semiconductor device adapted for mounting on a substrate
07/16/2002US6420787 Semiconductor device and process of producing same
07/16/2002US6420786 Conductive spacer in a via
07/16/2002US6420785 Bus line wiring structure in a semiconductor device and method of manufacturing the same
07/16/2002US6420783 Semiconductor device and a method of manufacturing the same
07/16/2002US6420782 Vertical ball grid array integrated circuit package
07/16/2002US6420780 Voltage regulator
07/16/2002US6420779 Leadframe based chip scale package and method of producing the same
07/16/2002US6420778 Differential electrical transmission line structures employing crosstalk compensation and related methods
07/16/2002US6420773 Multi-level spiral inductor structure having high inductance (L) and high quality factor (Q)
07/16/2002US6420772 Re-settable tristate programmable device
07/16/2002US6420762 Integrated electrostatic protective resistor for metal oxide semiconductor field effect transistors (MOSFETs)
07/16/2002US6420755 Semiconductor device having a field effect transistor and a method of manufacturing such a device
07/16/2002US6420725 Method and apparatus for forming an integrated circuit electrode having a reduced contact area
07/16/2002US6420664 Metal foil having bumps, circuit substrate having the metal foil, and semiconductor device having the circuit substrate
07/16/2002US6420663 One layer spider interconnect
07/16/2002US6420661 Connector element for connecting microelectronic elements
07/16/2002US6420660 Film used as a substrate for integrated circuits
07/16/2002US6420441 Dispersing removable crosslinked polymer porogens in a polysiloxane, curing, and heating to remove porogen; low dielectric constant; high porosity; insulation materials
07/16/2002US6420262 Coating insulator and conductor barrier layers on semiconductors to prevent migration, electrical resistance and capacitance; vapor deposition
07/16/2002US6420260 Ti/Tinx underlayer which enables a highly <111> oriented aluminum interconnect
07/16/2002US6420254 Recessed bond pad
07/16/2002US6420253 Thiol or sulfur portion of an alkyl mercaptan or a disulfide derivative bonds with a noble metal, alkyl portion is oriented away from the surface
07/16/2002US6420251 Coating conductor layers on dielectrics, etching patterns, appyling silicon oxide and a polyarylcyclobutene, then etching to form surface flatness; semiconductors
07/16/2002US6420244 Method of making wafer level chip scale package
07/16/2002US6420227 Semiconductor integrated circuit device and process for manufacture of the same
07/16/2002US6420224 Stepper alignment mark formation with dual field oxide process
07/16/2002US6420217 Method of an apparatus for programming an integrated fuse element to high resistance in low voltage technology
07/16/2002US6420216 Fuse processing using dielectric planarization pillars
07/16/2002US6420214 Polycyanurates
07/16/2002US6420212 Method and apparatus to enclose dice
07/16/2002US6420211 Method for protecting an integrated circuit chip
07/16/2002US6420209 Integrated circuits and methods for their fabrication
07/16/2002US6420208 Method of forming an alternative ground contact for a semiconductor die
07/16/2002US6420207 Full body gold; improved electrical and mechanical connects; copper circuit on wire bond side is fully covered, solder mask applied directly to semiconductor to avoid contact with gold; ball area protected by metall or an organic solderable
07/16/2002US6420204 Method of making a plastic package for an optical integrated circuit device
07/16/2002US6420201 Method for forming a bond wire pressure sensor die package
07/16/2002US6420189 High density semiconductors with deep submicron features which require low rlc delay interconnections between active devices; y--ba--cu--o superconductor formed in a cavity in dielectric; electrodepositing a y--ba--cu alloy; annealing in oxygen flow
07/16/2002US6420096 Less metal is required compared to other thin film methods; metallic base layer, photoresist layer, electroconductive layer on exposed regions; photoresist is removed and the metallic base layer is etched
07/16/2002US6420018 Low thermal expansion circuit board and multilayer wiring circuit board
07/16/2002US6420017 Preventing the burst or void phenomenon of a copper paste, through hole copper clad laminates with a paper phenol or a paper epoxy used as a base; discharging out gas from the through hole
07/16/2002US6419980 Process for producing an automatic-machine-bondable ceramic circuit carrier, and automatic-machine-bondable ceramic circuit carrier
07/16/2002US6419406 Optomodule
07/16/2002US6419008 CPU cooling device with a mounting mechanism