Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 23 - Details of semiconductor or other solid state devices
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
08/2002
08/28/2002EP1234314A1 Inductor on integrated circuit and methods for manufacture
08/28/2002EP1233935A1 Method for attaching a body, which is comprised of a metal matrix composite (mmc) material, to a ceramic body
08/28/2002EP0993653B1 Method and arrangement for protecting electronic computing units, in particular chip cards
08/28/2002CN2508397Y Multiple group lug-to-lug packing structure
08/28/2002CN2508396Y Conductive member of integrated circuit socket
08/28/2002CN2508395Y 热交换模组 Heat exchange module
08/28/2002CN2508394Y Heat-sink for computer
08/28/2002CN2508393Y CPU heat-sink assembly device
08/28/2002CN2508392Y Low stress chip assembly
08/28/2002CN2508280Y Common heat radiator base
08/28/2002CN1366708A Reinforcement material for silicon wafer and method of manufacturing IC chip using reinforcement material
08/28/2002CN1366686A Laminated body, capacitor, electronic part, and method and device for manufacturing the same
08/28/2002CN1366448A Cooling device of cooling exothermic element and electron equipment having said cooling device
08/28/2002CN1366446A Parts built in module and its making method
08/28/2002CN1366444A Parts built-in module and its making method
08/28/2002CN1089790C Pressure-sensitive adhesive having excellent heat resistance and heat conductivity, adhesive sheets, and method of securing electronic component to heat-radiating member therewith
08/28/2002CN1089652C Intermediate material for producing dual gauge strip and method for producing same and method for producing dual guage strip
08/27/2002US6442057 Memory module for preventing skew between bus lines
08/27/2002US6442043 Chip assembly module of bump connection type using a multi-layer printed circuit substrate
08/27/2002US6442042 Circuit configuration having at least one nanoelectronic component and method for fabricating the component
08/27/2002US6442041 MCM—MLC technology
08/27/2002US6442040 Embedded memory assembly
08/27/2002US6442033 Low-cost 3D flip-chip packaging technology for integrated power electronics modules
08/27/2002US6442026 Apparatus for cooling a circuit component
08/27/2002US6442025 Cooling unit for cooling heat generating component and electronic apparatus having the cooling unit
08/27/2002US6442023 Electronic power device
08/27/2002US6441943 Indicators and illuminators using a semiconductor radiation emitter package
08/27/2002US6441676 Externally programmable antifuse
08/27/2002US6441520 Power module
08/27/2002US6441504 Precision aligned and marked structure
08/27/2002US6441503 Bond wire pressure sensor die package
08/27/2002US6441502 Member for mounting of semiconductor
08/27/2002US6441500 Semiconductor device having resin members provided separately corresponding to externally connecting electrodes
08/27/2002US6441499 Thin form factor flip chip ball grid array
08/27/2002US6441498 Semiconductor substrate and land grid array semiconductor package using same
08/27/2002US6441497 Semiconductor device fabricated on multiple substrates and method for fabricating the same
08/27/2002US6441495 Semiconductor device of stacked chips
08/27/2002US6441494 Microelectronic contacts
08/27/2002US6441493 Circuit board having interconnection ball lands and ball grid array (BGA) package using the circuit board
08/27/2002US6441492 Diffusion barriers for copper interconnect systems
08/27/2002US6441491 Ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device containing the same
08/27/2002US6441490 Low dielectric constant stop layer for integrated circuit interconnects
08/27/2002US6441489 Semiconductor device with tantalum nitride barrier film
08/27/2002US6441488 Fan-out translator for a semiconductor package
08/27/2002US6441487 Chip scale package using large ductile solder balls
08/27/2002US6441486 BGA substrate via structure
08/27/2002US6441485 Apparatus for electrically mounting an electronic device to a substrate without soldering
08/27/2002US6441484 Semiconductor device having switching elements around a central control circuit
08/27/2002US6441483 Die stacking scheme
08/27/2002US6441481 Hermetically sealed microstructure package
08/27/2002US6441480 Microelectronic circuit package
08/27/2002US6441479 System-on-a-chip with multi-layered metallized through-hole interconnection
08/27/2002US6441478 Semiconductor package having metal-pattern bonding and method of fabricating the same
08/27/2002US6441477 Substrate mounting an integrated circuit package with a deformed lead
08/27/2002US6441476 Flexible tape carrier with external terminals formed on interposers
08/27/2002US6441475 Chip scale surface mount package for semiconductor device and process of fabricating the same
08/27/2002US6441474 Semiconductor device and liquid crystal module adopting the same
08/27/2002US6441473 Flip chip semiconductor device
08/27/2002US6441472 Semiconductor device and method of manufacturing the same
08/27/2002US6441471 Wiring substrate for high frequency applications
08/27/2002US6441470 Technique to minimize crosstalk in electronic packages
08/27/2002US6441467 Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film
08/27/2002US6441465 Scribe line structure for preventing from damages thereof induced during fabrication
08/27/2002US6441457 Fuse in semiconductor device and fabricating method thereof
08/27/2002US6441456 Semiconductor device and a process for manufacturing the same
08/27/2002US6441452 Method of reducing defects in anti-reflective coatings and semiconductor structures fabricated thereby
08/27/2002US6441442 Integrated inductive circuits
08/27/2002US6441420 Semiconductor device and method of fabricating the same
08/27/2002US6441419 Encapsulated-metal vertical-interdigitated capacitor and damascene method of manufacturing same
08/27/2002US6441418 Spacer narrowed, dual width contact for charge gain reduction
08/27/2002US6441416 Resin-encapsulated semiconductor apparatus and process for its fabrication
08/27/2002US6441407 Gate controlled thyristor driven with low-inductance
08/27/2002US6441402 Optical electronic apparatus and method for producing the same
08/27/2002US6441400 Semiconductor device and method of fabricating the same
08/27/2002US6441397 Evaluation of semiconductor chargeup damage and apparatus therefor
08/27/2002US6441396 In-line electrical monitor for measuring mechanical stress at the device level on a semiconductor wafer
08/27/2002US6441320 Electrically conductive projections having conductive coverings
08/27/2002US6441317 Semiconductor module and inverter device
08/27/2002US6441316 Printed-circuit board and a semiconductor module, and a manufacturing process of the semiconductor module
08/27/2002US6441314 Multilayered substrate for semiconductor device
08/27/2002US6441313 Printed circuit board employing lossy power distribution network to reduce power plane resonances
08/27/2002US6441312 Electronic package with plurality of solder-applied areas providing heat transfer
08/27/2002US6441014 Antiinflammatory agent, useful for treating cylcoocygenase-2 associated disorders
08/27/2002US6440878 Plasma enhanced chemical vapor deposition (pecvd) process is provided for depositing one or more dielectric material layers on a substrate for use in interconnect structures of integrated circuits
08/27/2002US6440870 Accuracy control of etching using plasma
08/27/2002US6440854 Deposited by physical vapor deposition
08/27/2002US6440852 Integrated circuit including passivated copper interconnection lines and associated manufacturing methods
08/27/2002US6440851 Method and structure for controlling the interface roughness of cobalt disilicide
08/27/2002US6440850 Structure for an electrical contact to a thin film in a semiconductor structure and method for making the same
08/27/2002US6440849 Substantially eliminates the grain growth of copper due to self annealing;
08/27/2002US6440848 Low resistance.
08/27/2002US6440846 Method for forming semiconductor device
08/27/2002US6440845 Method of fabricating interconnect of capacitor
08/27/2002US6440844 Semiconductor device with copper wiring and its manufacture method
08/27/2002US6440836 Method for forming solder bumps on flip chips and devices formed
08/27/2002US6440834 Forming dielectric layer on surface of semiconductor, forming first and second conductive lines in first dielectric layer, forming second dielectric layer covering first and second conductive lines, forming hole, filling with fuse material
08/27/2002US6440833 Method of protecting a copper pad structure during a fuse opening procedure
08/27/2002US6440831 Ionized metal plasma deposition process having enhanced via sidewall coverage
08/27/2002US6440827 Method for fabricating a semiconductor component having a wiring which runs piecewise in the substrate, and also a semiconductor component which can be fabricated by this method
08/27/2002US6440822 Method of manufacturing semiconductor device with sidewall metal layers
1 ... 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 ... 2262