| Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155) |
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| 09/04/2002 | CN1090440C Method for cleaning metal masks for surface mounting technology |
| 09/04/2002 | CN1090439C Method for preparing base plate for semiconductor assembling |
| 09/04/2002 | CN1090438C Hand-off method in personal communication service system |
| 09/04/2002 | CN1090220C Adhesive sheet for wafer and process for preparing semiconductor apparatus using the same |
| 09/04/2002 | CN1090219C Solventless liminating adhesive with barrier properties |
| 09/03/2002 | US6446033 Method for simulating electrical characteristics of electronic device |
| 09/03/2002 | US6445594 Semiconductor device having stacked semiconductor elements |
| 09/03/2002 | US6445583 Snap in heat sink shielding lid |
| 09/03/2002 | US6445580 Adaptable heat dissipation device for a personal computer |
| 09/03/2002 | US6445564 Power supply bypass capacitor circuit for reducing power supply noise and semiconductor integrated circuit device having the capacitor circuit |
| 09/03/2002 | US6445255 Planar dielectric integrated circuit |
| 09/03/2002 | US6445242 Fuse selectable pinout package |
| 09/03/2002 | US6445199 Methods and apparatus for generating spatially resolved voltage contrast maps of semiconductor test structures |
| 09/03/2002 | US6445194 Structure and method for electrical method of determining film conformality |
| 09/03/2002 | US6445077 Semiconductor chip package |
| 09/03/2002 | US6445076 Insulating adhesive for electronic parts, and lead frame and semiconductor device using the same |
| 09/03/2002 | US6445071 Semiconductor device having an improved multi-layer interconnection structure and manufacturing method thereof |
| 09/03/2002 | US6445070 Coherent carbide diffusion barrier for integrated circuit interconnects |
| 09/03/2002 | US6445069 Electroless Ni/Pd/Au metallization structure for copper interconnect substrate and method therefor |
| 09/03/2002 | US6445067 Integrated circuit package electrical enhancement |
| 09/03/2002 | US6445066 Splitting and assigning power planes |
| 09/03/2002 | US6445065 Routing driven, metal programmable integrated circuit architecture with multiple types of core cells |
| 09/03/2002 | US6445064 Semiconductor device |
| 09/03/2002 | US6445062 Semiconductor device having a flip chip cavity with lower stress and method for forming same |
| 09/03/2002 | US6445061 Leads under chip in conventional IC package |
| 09/03/2002 | US6445060 Coated semiconductor die/leadframe assembly and method for coating the assembly |
| 09/03/2002 | US6445056 Semiconductor capacitor device |
| 09/03/2002 | US6445055 Semiconductor integrated circuit device and manufacturing method thereof |
| 09/03/2002 | US6445050 Symmetric device with contacts self aligned to gate |
| 09/03/2002 | US6445039 System and method for ESD Protection |
| 09/03/2002 | US6445023 Diffusion barriers |
| 09/03/2002 | US6445018 Semiconductor device having signal line above main ground or main VDD line, and manufacturing method thereof |
| 09/03/2002 | US6445013 Gate commutated turn-off semiconductor device |
| 09/03/2002 | US6445004 Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof |
| 09/03/2002 | US6445001 Semiconductor device with flip-chip structure and method of manufacturing the same |
| 09/03/2002 | US6444924 Printed wiring board with joining pin and manufacturing method therefor |
| 09/03/2002 | US6444921 Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like |
| 09/03/2002 | US6444919 Thin film wiring scheme utilizing inter-chip site surface wiring |
| 09/03/2002 | US6444918 Interconnection structure of semiconductor element |
| 09/03/2002 | US6444905 Semiconductor device |
| 09/03/2002 | US6444593 Depleting fluorine from surface of fluorinated silicon dioxide dielectric material disposed between first metal stack and second metal stack utilizing ammonia, passivating surface utilizing nitrous oxide |
| 09/03/2002 | US6444580 Method of reducing carbon, sulphur, and oxygen impurities in a calcium-doped copper surface and semiconductor device thereby formed |
| 09/03/2002 | US6444568 Method of forming a copper diffusion barrier |
| 09/03/2002 | US6444565 Dual-rie structure for via/line interconnections |
| 09/03/2002 | US6444563 Method and apparatus for extending fatigue life of solder joints in a semiconductor device |
| 09/03/2002 | US6444560 Making connections between chips by using matching stud/via structures, fabricating device having dense arrangement of chips and high wiring density of chip-to-chip interconnections |
| 09/03/2002 | US6444558 Methods of forming and programming junctionless antifuses |
| 09/03/2002 | US6444544 Method of forming an aluminum protection guard structure for a copper metal structure |
| 09/03/2002 | US6444530 Process for fabricating an integrated circuit with a self-aligned contact |
| 09/03/2002 | US6444515 Forming on semiconductor substrate gate electrode, hard mask insulating layer, thin insulating layer, nitride stopper layer, sidewall nitride layer, interlayer insulating layer, and interconnection layer formed in contact hole in interlayer |
| 09/03/2002 | US6444503 First patterned dielectric layer is formed over the substrate. |
| 09/03/2002 | US6444502 Dielectric layer which is deposited over a metal layer. the semiconductor substrate is then masked and etched so as to form openings in the dielectric layer. metal is deposited over the semiconductor substrate and is polished so as to |
| 09/03/2002 | US6444501 Two stage transfer molding method to encapsulate MMC module |
| 09/03/2002 | US6444500 Resin-encapsulating a substrate on which a plurality of semiconductor chips are formed, includes a first mold and a second mold. the second mold has a pressing surface that is provided with a mold release sheet. |
| 09/03/2002 | US6444499 The snapable multi-package substrate is formed with trenches that separate and define sections where individual packaged electronic components are fabricated in a snapable multi-package array, and where individual packaged electronic |
| 09/03/2002 | US6444498 Method of making semiconductor package with heat spreader |
| 09/03/2002 | US6444497 Method and apparatus for reducing BGA warpage caused by encapsulation |
| 09/03/2002 | US6444496 Introducing thermal paste into semiconductor packages. the invention encompasses an apparatus and a method that uses at least one preform of thermal paste for the cooling of at least one chip in a sealed semiconductor package. |
| 09/03/2002 | US6444495 A colloidal suspension of nanoparticles composed of a dense material dispersed in a solvent is used in forming a gap-filling dielectric material with low thermal shrinkage. the dielectric material is particularly useful for pre-metal |
| 09/03/2002 | US6444494 Separating individual film substrates from a film substrate tape having a plurality of said film substrates continuously and integrally connected to and second surfaces, a circuit pattern being formed on said first surface and a mounting |
| 09/03/2002 | US6444490 Micro-flex technology in semiconductor packages |
| 09/03/2002 | US6444489 Semiconductor chip assembly with bumped molded substrate |
| 09/03/2002 | US6444484 Fabricating a semiconductor device on a substrate comprising the steps of: forming a first conductive layer on the substrate; forming an insulation layer on the first conductive layer;and a second conductive layer with overlapping and |
| 09/03/2002 | US6444481 Measuring a thickness of the process layer; and determining at least one plating parameter of the recipe for subsequently formed process layers based on the measured thickness. a processing line includes a plating tool, a metrology tool, |
| 09/03/2002 | US6444371 An apparatus used for forming dummy die features on semiconductor wafers, said apparatus comprising: mask reticle having a die array of integrated circuit patterns; die array and targets geometric shapes placed in blank stepping fields |
| 09/03/2002 | US6444295 Multilayer; dielectric substrate, bonding pad, passivation layer, coupling wires |
| 09/03/2002 | US6443743 Method for reducing via resistance in small high aspect ratio holes filled using aluminum extrusion |
| 09/03/2002 | US6443741 Socket for electrical parts |
| 09/03/2002 | US6443720 Apparatus for filling a gap between spaced layers of a semiconductor |
| 09/03/2002 | US6443298 Surface package type semiconductor package and method of producing semiconductor memory |
| 09/03/2002 | US6443222 Cooling device using capillary pumped loop |
| 09/03/2002 | US6442990 Method of manufacturing a plate-shaped member having a recess and press die for forming recesses |
| 09/03/2002 | US6442816 Tool for mounting clip to CPU socket |
| 09/03/2002 | CA2260305C Electronic apparatus |
| 09/03/2002 | CA2230903C Mounting assembly of integrated circuit device and method for production thereof |
| 08/29/2002 | WO2002067640A1 Electronic device and method of manufacturing the same |
| 08/29/2002 | WO2002067639A1 An electronic device and a circuit arrangement |
| 08/29/2002 | WO2002067326A2 Integrated circuit die having an electromagnetic interference shield |
| 08/29/2002 | WO2002067325A2 High-density flip-chip interconnect |
| 08/29/2002 | WO2002067324A1 Member for electronic circuit, method for manufacturing the member, and electronic part |
| 08/29/2002 | WO2002067323A1 Semiconductor device and its cooling surface forming method |
| 08/29/2002 | WO2002067322A2 Semiconductor device having signal contacts and high current power contacts |
| 08/29/2002 | WO2002067321A2 Enhanced die-down ball grid array and method for making the same |
| 08/29/2002 | WO2002067319A2 Copper interconnect structure having diffusion barrier |
| 08/29/2002 | WO2002067318A2 Electromigration test structure for determining the reliability of wiring |
| 08/29/2002 | WO2002067317A1 Bumpless semiconductor device |
| 08/29/2002 | WO2002067315A2 Processes of forming thermal transfer materials, and thermal transfer materials |
| 08/29/2002 | WO2002067299A2 Method and related apparatus of processing a substrate |
| 08/29/2002 | WO2002067292A2 Semiconductor package and method of preparing same |
| 08/29/2002 | WO2002067291A2 Arrangement of a semi-conductor chip on a substrate |
| 08/29/2002 | WO2002067180A1 On-the-fly beam path error correction for memory link processing |
| 08/29/2002 | WO2002066534A1 Liquid epoxy resin emulsions, method for the production and use thereof |
| 08/29/2002 | WO2002066256A2 Process for the manufacture of printed circuit boards with plated resistors |
| 08/29/2002 | WO2002041679A3 Electromagnetic shielding and cooling device for printed circuit board |
| 08/29/2002 | WO2002041396A3 High performance heat sink configurations for use in high density packaging applications |
| 08/29/2002 | WO2002039483A3 Single metal programmability in a customizable integrated circuit device |
| 08/29/2002 | WO2002019422A3 Method for manufacturing diode subassemblies used in rectifier assemblies of engine driven generators |
| 08/29/2002 | WO2001099148A3 Electrical fuses employing reverse biasing to enhance programming |
| 08/29/2002 | WO2001088976B1 Wireless radio frequency testing methode of integrated circuits and wafers |
| 08/29/2002 | US20020119677 Semiconductor device manufacturing method |