Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 23 - Details of semiconductor or other solid state devices
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
09/2002
09/12/2002WO2002070977A1 Heat exchanger having fins
09/12/2002WO2002070191A1 Fluxing underfill compositions
09/12/2002WO2002019430A3 Hybrid substrate with embedded capacitors and methods of manufacture
09/12/2002WO2002013268A3 Module, especially a wafer module
09/12/2002WO2001068304A3 Flip chip-in-leadframe package and process
09/12/2002US20020128397 Phenolic resins modified with phosphorus oxychloride (POCl3) of given formula; flame retardant properties and high heat resistance so as not to require additional flame retardants; use as electronic packaging material
09/12/2002US20020128354 The addition of polybenzoxazines as a co-reactant with one or several epoxy resins provides a product with reduced moisture adsorption while maintaining a high glass transition temperature; encapsulation of microchips
09/12/2002US20020128353 Epoxy resin; acidic fluxing agent; anhydride; latent curing agent component comprising a complex of a portion of the acidic fluxing agent and a salt of a nitrogen-containing component.
09/12/2002US20020127924 Covering sheet, triplate line using the sheet, signal bus for computer using the sheet and covering structure of electronic circuit using the sheet
09/12/2002US20020127900 Electrical and fluid interconnect
09/12/2002US20020127893 Particle distribution interposer and method of manufacture thereof
09/12/2002US20020127880 Production method of semiconductor device
09/12/2002US20020127868 Integrated circuits and methods for their fabrication
09/12/2002US20020127851 Method of producing semiconductor device
09/12/2002US20020127850 Integrated circuit with stop layer and method of manufacturing the same
09/12/2002US20020127848 Semiconductor device and method of manufacturing the same
09/12/2002US20020127846 Copper to aluminum interlayer interconnect using stud and via liner
09/12/2002US20020127843 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
09/12/2002US20020127842 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
09/12/2002US20020127839 Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument
09/12/2002US20020127837 Methods for forming a die package
09/12/2002US20020127835 Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same
09/12/2002US20020127834 Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
09/12/2002US20020127825 Method of preparing copper metallization die for wirebonding
09/12/2002US20020127815 Method for forming protrusive alignment-mark
09/12/2002US20020127807 Semiconductor device, semiconductor wafer, and methods of producing the same device and wafer
09/12/2002US20020127792 Optimum surface orientation of the silicon substrate and optimum orientation for epitaxial growth when the layer of a group III nitride compound semiconductor is formed on the silicon substrate by using epitaxial growth.
09/12/2002US20020127782 Wiring method in layout design of semiconductor integrated circuit, semiconductor integrated circuit and functional macro
09/12/2002US20020127780 Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
09/12/2002US20020127779 Chip scale package and manufacturing method thereof
09/12/2002US20020127778 Easy loading; improved sealing
09/12/2002US20020127777 Semiconductor device and manufacturing method thereof
09/12/2002US20020127776 Semiconductor device having an organic material layer and method for making the same
09/12/2002US20020127775 Redistributed bond pads in stacked integrated circuit die package
09/12/2002US20020127774 Flip-chip semiconductor package structure and process for fabricating the same
09/12/2002US20020127773 Production of semiconductor device
09/12/2002US20020127771 Multiple die package
09/12/2002US20020127770 Die support structure
09/12/2002US20020127769 Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
09/12/2002US20020127768 Compliant wafer-level packaging devices and methods of fabrication
09/12/2002US20020127766 Semiconductor wafer manufacturing process
09/12/2002US20020127765 Minitab rectifier for alternators
09/12/2002US20020127746 Gallium phosphide single-crystalline substrate at least one each of n-type gallium phosphide layer and p-type gallium phosphide layer
09/12/2002US20020127494 Providing perforate metal core; applying a dielectric polymer onto all exposed surfaces; applying a dielectric polymer; ablating surface of dielectric polymer in a pattern to expose; forming metallized vias; applying photosensitive layer
09/12/2002US20020127486 Suitable for a pattern formation on a semiconductor wafer
09/12/2002US20020127483 For use in semiconductor device
09/12/2002US20020127418 Embedding resin and wiring substrate using the same
09/12/2002US20020126465 EMI reduction in power modules through the use of integrated capacitors on the substrate level
09/12/2002US20020126464 Noise protection sheet
09/12/2002US20020126460 Printed circuit board arrangement
09/12/2002US20020126459 Stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
09/12/2002US20020126453 Apparatus for cooling an electronic component and electronic device comprising the apparatus
09/12/2002US20020126452 Heat sink chip package
09/12/2002US20020126451 Retaining clamp for cooling fins
09/12/2002US20020125931 System for providing electrostatic discharge protection for high-speed integrated circuits
09/12/2002US20020125612 Method for production of three-dimensionally arranged conducting and connecting structures for volumetric and energy flows
09/12/2002US20020125580 Stacked semiconductor chip package
09/12/2002US20020125579 Semiconductor device having damascene interconnection structure that prevents void formation between interconnections
09/12/2002US20020125577 Semiconductor integrated circuit device with moisture-proof ring and its manufacture method
09/12/2002US20020125576 Semiconductor device
09/12/2002US20020125575 Semiconductor device and method of producing the same
09/12/2002US20020125574 Multi-layer conductor system with intermediate buffer layer for improved adhesion to dielectrics
09/12/2002US20020125572 Semiconductor device having no cracks in one or more layers underlying a metal line layer and method of manufacturing the same
09/12/2002US20020125571 Module assembly for stacked BGA packages
09/12/2002US20020125570 Ball grid array semiconductor package structure to avoid high frequency interference
09/12/2002US20020125569 Semiconductor device with bumps for pads
09/12/2002US20020125568 Method Of Fabricating Chip-Scale Packages And Resulting Structures
09/12/2002US20020125567 Die support structure
09/12/2002US20020125566 High frequency circuit chip and method of producing the same
09/12/2002US20020125565 Semiconductor device
09/12/2002US20020125564 Semiconductor device reinforced by a highly elastic member made of a synthetic resin
09/12/2002US20020125563 Power semiconductor module of high isolation strength
09/12/2002US20020125562 Attaching semiconductor dies to substrates with conductive straps
09/12/2002US20020125561 Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument
09/12/2002US20020125560 Semiconductor device formed by mounting semiconductor chip on support substrate, and the support substrate
09/12/2002US20020125559 Enhanced leadless chip carrier
09/12/2002US20020125557 Package of a chip with beveled edges
09/12/2002US20020125556 Stacking structure of semiconductor chips and semiconductor package using it
09/12/2002US20020125555 Semiconductor device and communication terminal using thereof
09/12/2002US20020125554 Semiconductor device
09/12/2002US20020125553 Method of packaging a device with a lead frame, and an apparatus formed therefrom
09/12/2002US20020125551 Micro bubble grid array semiconductor package
09/12/2002US20020125550 Dual stacked die package
09/12/2002US20020125549 Low k dielectric materials with inherent copper ion migration barrier
09/12/2002US20020125546 Semiconductor device, production method therefor, and electrophotographic apparatus
09/12/2002US20020125537 Integrated radio frequency circuits
09/12/2002US20020125534 Semiconductor device having silicon-on-insulator structure and method of fabricating the same
09/12/2002US20020125533 Thin film transistor substrate and process for producing the same
09/12/2002US20020125512 Semiconductor device and manufacturing method thereof
09/12/2002US20020125505 Substrate for an electronic power circuit, and an electronic power module using such a substrate
09/12/2002US20020125477 Thin film transistors with dual layered source/drain electrodes and manufacturing method thereof, and active matrix display device and manufacturing method thereof
09/12/2002US20020125329 Electronic module for chip card
09/12/2002US20020125228 Energy-efficient method and system for processing target material using an amplified, wavelength-shifted pulse train
09/12/2002US20020125206 Depositing metal film including an aluminum over a semiconductor substrate, and etching the metal film with a plasma of a gas mixture containing chlorine, boron trichloride and dichloromethane
09/12/2002US20020125124 Method for shorting pin grid array pins for plating
09/12/2002US20020125123 Titanium nitride film having a resistivity of less than about 75 mu Omega-cm; surface smoothness; made by controlling the gas phase deposition mixture, and controlling deposition rate
09/12/2002US20020125044 Layered circuit boards and methods of production thereof
09/12/2002US20020125043 Semiconductor packaging structure, packaging board and inspection method of packaging conditions
09/12/2002US20020125042 Method for transforming a substrate with edge contacts into a ball grid array, ball grid array manufactured according to this method, and flexible wiring for the transformation of a substrate with edge contacts into a ball grid array
09/12/2002US20020125041 Package base for mounting electronic element, electronic device and method of producing the same
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