Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
12/2002
12/03/2002US6489676 Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
12/03/2002US6489674 Method for creating a die shrink insensitive semiconductor package and component therefor
12/03/2002US6489672 Integrated circuit package architecture with improved electrostatic discharge protection
12/03/2002US6489671 Semiconductor integrated circuit having three-dimensional interconnection lines
12/03/2002US6489670 Sealed symmetric multilayered microelectronic device package with integral windows
12/03/2002US6489669 Integrated circuit device
12/03/2002US6489668 Semiconductor device and method for manufacturing the same
12/03/2002US6489667 Semiconductor device and method of manufacturing such device
12/03/2002US6489663 Spiral inductor semiconducting device with grounding strips and conducting vias
12/03/2002US6489662 Semiconductor integrated circuit device formed on SOI substrate
12/03/2002US6489656 Resistor for high performance system-on-chip using post passivation process
12/03/2002US6489652 Trench DMOS device having a high breakdown resistance
12/03/2002US6489647 Capacitor for high performance system-on-chip using post passivation process structure
12/03/2002US6489640 Integrated circuit with fuse element and contact pad
12/03/2002US6489637 Hybrid integrated circuit device
12/03/2002US6489634 Microelectronic device structure utilizing a diamond inlay in a package flange
12/03/2002US6489573 Electrode bonding structure for reducing the thermal expansion of the flexible printed circuit board during the bonding process
12/03/2002US6489572 Substrate structure for an integrated circuit package and method for manufacturing the same
12/03/2002US6489571 Molded tape ball grid array package
12/03/2002US6489564 Stress relieving tape bonding interconnect
12/03/2002US6489558 Conductive cap, electronic component, and method of forming insulating film of conductive cap
12/03/2002US6489557 Method of implementing micro bga. more specifically, the present invention discloses a method of packaging an integrated circuit into an integrated circuit assembly. the method of the present invention first mounts polyimide tape to
12/03/2002US6489551 Electronic module with integrated thermoelectric cooling assembly
12/03/2002US6489380 Mixtures of fillers, heterocylic ethers, nitriles, lewis acid catalysts and/or brownsted acids having high flexibility and hermetic sealing, used in semiconductor applications
12/03/2002US6489244 Fuse, memory incorporating same and method
12/03/2002US6489230 Integration of low-k SiOF as inter-layer dielectric
12/03/2002US6489228 Integrated electronic device comprising a mechanical stress protection structure
12/03/2002US6489227 Method of etching a polysilicon layer during the stripping of the photoresist shape used as an etch mask to create an opening to an underlying fuse structure
12/03/2002US6489219 Method of alloying a semiconductor device
12/03/2002US6489218 Singulation method used in leadless packaging process
12/03/2002US6489216 Chemical mechanical polish (CMP) planarizing method employing topographic mark preservation
12/03/2002US6489208 Method of forming a laminated structure to enhance metal silicide adhesion on polycrystalline silicon
12/03/2002US6489186 Adhesion enhanced semiconductor die for mold compound packaging
12/03/2002US6489183 Method of manufacturing a taped semiconductor device
12/03/2002US6489182 Method of fabricating a wire arrayed chip size package
12/03/2002US6489181 Method of manufacturing a semiconductor device
12/03/2002US6489180 Flip-chip packaging process utilizing no-flow underfill technique
12/03/2002US6489178 Method of fabricating a molded package for micromechanical devices
12/03/2002US6489173 Method for determining lead span and planarity of semiconductor devices
12/03/2002US6489042 Covercoats to protect the circuitry
12/03/2002US6489030 Low dielectric constant films used as copper diffusion barrier
12/03/2002US6489013 Polyamideimide with siloxane bonds, high molecular weight acrylic polymer, thermoset resin and solvent; low thermal stress and modulus of elasticity; heat resistance
12/03/2002US6489007 Stereolithographically marked semiconductor devices and methods
12/03/2002US6489005 Method of making silicon article having columns
12/03/2002US6488984 Forming barrier and conductive metal layers under an environment shutoff from air; pyrolytic decomposition of such as copper from organometallic compound; low resistance; good adhesion
12/03/2002US6488879 Method of producing an electronic device having a sheathed body
12/03/2002US6488823 Stress tunable tantalum and tantalum nitride films
12/03/2002US6488795 Multilayered ceramic substrate and method of producing the same
12/03/2002US6488522 Socket for electric part
12/03/2002US6488513 Interposer assembly for soldered electrical connections
12/03/2002US6488198 Wire bonding method and apparatus
11/2002
11/28/2002WO2002096172A1 Method for manufacturing ceramic multilayered board
11/28/2002WO2002096164A2 Method for shielding an electric circuit created on a printed circuit board and a corresponding combination of a printed circuit board and a shield
11/28/2002WO2002095969A1 Millimeter wave transceiver module
11/28/2002WO2002095879A1 A high frequency, low cost package for semiconductor devices
11/28/2002WO2002095826A2 Photonic and electronic components on a shared substrate
11/28/2002WO2002095825A2 Laser-assisted silicide fuse programming
11/28/2002WO2002095824A1 Power source circuit device
11/28/2002WO2002095823A2 High performance air cooled heat sinks used in high density packaging applications
11/28/2002WO2002095822A2 Method for packaging a microelectronic device using on-die bond pad expansion
11/28/2002WO2002095821A2 Housing for a photoactive semiconductor chip and a method for the production thereof
11/28/2002WO2002095817A2 Semiconductor component with at least one semiconductor chip on a base chip serving as substrate and method for production thereof
11/28/2002WO2002095801A2 Improved connection assembly for integrated circuit sensors
11/28/2002WO2002095796A2 Optical semiconductor housing with incorporated lens and shielding
11/28/2002WO2002095785A1 Raised on-chip inductor and method of manufacturing same
11/28/2002WO2002095673A1 Lead-frame configuration for chips
11/28/2002WO2002080226A3 Bonding pad for flip-chip fabrication
11/28/2002WO2002055942A3 Normal-flow heat exchanger
11/28/2002WO2002049108A8 Semiconductor device package and lead frame with die overhanging lead frame pad
11/28/2002WO2002043142A3 Packaged electronic component and method for packaging an electronic component
11/28/2002WO2002039487A3 Device and method for encasing an electronic component
11/28/2002WO2002013271A3 Integrated electronic circuit with at least one inductor and method for producing the same
11/28/2002US20020178426 System for and method of efficient contact pad identification
11/28/2002US20020177360 Composite electronic component and method of producing same
11/28/2002US20020177344 Semiconductor device-socket
11/28/2002US20020177325 Method of manufacturing semiconductor device and semiconductor device
11/28/2002US20020177317 Immediate improvement of dewatering on paper machine; does not negatively affect web formation
11/28/2002US20020177307 Semiconductor device and a method for forming a via hole in a semiconductor device
11/28/2002US20020177306 Method to place a thermal interface when manufacturing an integrated circuit
11/28/2002US20020177302 Inhibition of atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure.
11/28/2002US20020177297 Method for forming wire in semiconductor device
11/28/2002US20020177294 Method of manufacturing a semiconductor device
11/28/2002US20020177291 Low dielectric constant polymers having good adhesion and toughness and articles made with such polymers
11/28/2002US20020177258 Chip on board and heat sink attachment methods
11/28/2002US20020177256 Method of making leadless semiconductor package
11/28/2002US20020177254 Semiconductor package and method for making the same
11/28/2002US20020176998 Doping with a second dopant an amorphous layer formed on a substrate including a semiconductor material and a first dopant, where second dopant is of polarity opposite the first dopant; spatial distribution of sheet resistance is measured
11/28/2002US20020176987 Ink comprising: a non-stoichiometric non-equilibrium nanostructured material; device such as electronics using such a material
11/28/2002US20020176972 Contact chain for testing and its relevantly debugging method
11/28/2002US20020176939 Method of improving the adhesion of copper
11/28/2002US20020176271 Reference plane of integrated circuit packages
11/28/2002US20020176239 Reference plane of integrated circuit packages
11/28/2002US20020176238 Multi-chip module having interconnect dies
11/28/2002US20020176233 Stackable module
11/28/2002US20020176230 Vertical surface mount apparatus with thermal carrier
11/28/2002US20020176229 Separable power delivery connector
11/28/2002US20020176228 Fixture assembly for a heat sink
11/28/2002US20020176227 Heat dispensing device for computers
11/28/2002US20020176032 Active matrix substrate for liquid crystal display and its fabrication
11/28/2002US20020175799 On-chip inductive structure