H01L 23 - Details of semiconductor or other solid state devices

Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
12/2002
12/18/2002	EP1266715A1 Gold wire bonding at room temperature
12/18/2002	EP1266405A1 Planarised semiconductor structure including a conductive fuse and process for fabrication thereof
12/18/2002	EP1266403A2 Method and device for connecting at least one chip to a rewiring arrangement
12/18/2002	EP1266402A2 Semiconductor element and method for producing the same
12/18/2002	EP1266399A2 Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
12/18/2002	EP1266397A2 Precision electroplated solder bumps and method for manufacturing thereof
12/18/2002	EP1265946A1 Poly(phenylene ether) - polyvinyl thermosetting resin
12/18/2002	CN2527069Y Efficient radiator
12/18/2002	CN2527029Y Power converter for railway locomotive
12/18/2002	CN2526980Y Zone electromagnetic interference preventing device for integrated circuit
12/18/2002	CN2526979Y Heat pipe radiator
12/18/2002	CN2526978Y 改良的组合式散热片 Improved modular fins
12/18/2002	CN2526977Y Chip radiating packaging structure
12/18/2002	CN2526976Y CPU heat radiator
12/18/2002	CN2526975Y Multi-layer substrate with voltage reference signal line distribution
12/18/2002	CN1386395A Circuit board and method for manufacturing the same, and electronic apparatus comprising it
12/18/2002	CN1386394A Flip chip package, circuit thereof and packaging method thereof
12/18/2002	CN1386303A Semiconductor device and method of manufacturing same
12/18/2002	CN1385902A Electrostatic discharge protective circuit
12/18/2002	CN1385900A Semiconductor package and making method thereof
12/18/2002	CN1096744C Electronic components and method of manufacturing same
12/18/2002	CN1096704C Semiconductor device including insulation film and fabrication method thereof
12/18/2002	CN1096685C Thick film conductor paste compositions for aluminium nitride substrates
12/17/2002	US6496968 Hierarchical wiring method for a semiconductor integrated circuit
12/17/2002	US6496959 Method and system for estimating plasma damage to semiconductor device for layout design
12/17/2002	US6496889 Chip-to-chip communication system using an ac-coupled bus and devices employed in same
12/17/2002	US6496416 Low voltage non-volatile memory cell
12/17/2002	US6496383 Integrated circuit carrier arrangement for reducing non-uniformity in current flow through power pins
12/17/2002	US6496375 Cooling arrangement for high density packaging of electronic components
12/17/2002	US6496374 Apparatus suitable for mounting an integrated circuit
12/17/2002	US6496373 Compressible thermally-conductive interface
12/17/2002	US6496372 Heat sink fastener for an electronic device
12/17/2002	US6496371 Heat sink mounting method and apparatus
12/17/2002	US6496370 Structure and method for an electronic assembly
12/17/2002	US6496369 Electronic apparatus having heat sink for cooling heat generating component
12/17/2002	US6496368 Heat-dissipating assembly having heat sink and dual hot-swapped fans
12/17/2002	US6496355 Interdigitated capacitor with ball grid array (BGA) terminations
12/17/2002	US6496118 Computer chip heat protection apparatus
12/17/2002	US6496053 Corrosion insensitive fusible link using capacitance sensing for semiconductor devices
12/17/2002	US6496035 Integrated circuit approach, with a serpentine conductor track for circuit configuration selection
12/17/2002	US6496016 Semiconductor device for use in evaluating integrated circuit device
12/17/2002	US6495928 Transfer mark structure for multi-layer interconnecting and method for the manufacture thereof
12/17/2002	US6495927 Resin-molded unit including an electronic circuit component
12/17/2002	US6495926 60 degree bump placement layout for an integrated circuit power grid
12/17/2002	US6495925 Semiconductor chip and a lead frame
12/17/2002	US6495924 Semiconductor device, including an arrangement to provide a uniform press contact and converter using same
12/17/2002	US6495922 Semiconductor device with pointed bumps
12/17/2002	US6495920 Wiring for semiconductor device
12/17/2002	US6495919 Conductive implant structure in a dielectric
12/17/2002	US6495918 Chip crack stop design for semiconductor chips
12/17/2002	US6495917 Method and structure of column interconnect
12/17/2002	US6495916 Resin-encapsulated semiconductor device
12/17/2002	US6495915 Flip chip package of monolithic microwave integrated circuit
12/17/2002	US6495914 Multi-chip module structure having conductive blocks to provide electrical connection between conductors on first and second sides of a conductive base substrate
12/17/2002	US6495913 Semiconductor clamped-stack assembly
12/17/2002	US6495912 Structure of ceramic package with integrated passive devices
12/17/2002	US6495911 Scalable high frequency integrated circuit package
12/17/2002	US6495910 Package structure for accommodating thicker semiconductor unit
12/17/2002	US6495909 Low-pin-count chip package and manufacturing method thereof
12/17/2002	US6495908 Multi-chip semiconductor package
12/17/2002	US6495907 Conductor reticulation for improved device planarity
12/17/2002	US6495902 Fuse for use in a semiconductor device, and semiconductor devices including the fuse
12/17/2002	US6495901 Multi-level fuse structure
12/17/2002	US6495895 Bi-level multilayered microelectronic device package with an integral window
12/17/2002	US6495889 Semiconductor device having self-aligned contacts
12/17/2002	US6495879 Ferroelectric memory device having a protective layer
12/17/2002	US6495874 Semiconductor device and production process thereof
12/17/2002	US6495870 Semiconductor device and method for patterning the semiconductor device in which line patterns terminate at different lengths to prevent the occurrence of a short or break
12/17/2002	US6495869 Method of manufacturing a double-heterojunction bipolar transistor on III-V material
12/17/2002	US6495860 Light emitting diode and manufacturing process thereof with blank
12/17/2002	US6495857 Thin film transister semiconductor devices
12/17/2002	US6495856 Semiconductor device having a test pattern same as conductive pattern to be tested and method for testing semiconductor device for short-circuit
12/17/2002	US6495772 High performance dense wire for printed circuit board
12/17/2002	US6495771 Compliant multi-layered circuit board for PBGA applications
12/17/2002	US6495770 Electronic assembly providing shunting of electrical current
12/17/2002	US6495768 Tape carrier package and method of fabricating the same
12/17/2002	US6495709 Nonaqueous organic precursor for forming aluminum oxide in solution
12/17/2002	US6495470 Contact and via fabrication technologies
12/17/2002	US6495466 Method of manufacturing a semiconductor device and a semiconductor device
12/17/2002	US6495462 Components with releasable leads
12/17/2002	US6495461 Process for forming amorphous titanium silicon nitride on substrate
12/17/2002	US6495454 Substrate interconnect for power distribution on integrated circuits
12/17/2002	US6495452 Method to reduce capacitance for copper interconnect structures
12/17/2002	US6495451 Method of forming interconnect
12/17/2002	US6495442 Post passivation interconnection schemes on top of the IC chips
12/17/2002	US6495441 Semiconductor device with gold bumps, and method and apparatus of producing the same
12/17/2002	US6495439 Method for suppressing pattern distortion associated with BPSG reflow and integrated circuit chip formed thereby
12/17/2002	US6495426 Method for simultaneous formation of integrated capacitor and fuse
12/17/2002	US6495409 MOS transistor having aluminum nitride gate structure and method of manufacturing same
12/17/2002	US6495408 Local interconnection process for preventing dopant cross diffusion in shared gate electrodes
12/17/2002	US6495400 Method of forming low profile semiconductor package
12/17/2002	US6495399 Method of vacuum packaging a semiconductor device assembly
12/17/2002	US6495397 Fluxless flip chip interconnection
12/17/2002	US6495396 Method of coupling and aligning semiconductor devices including multi-chip semiconductor devices
12/17/2002	US6495395 Electrical and thermal contact for use in semiconductor devices
12/17/2002	US6495394 Chip package and method for manufacturing the same
12/17/2002	US6495393 Method to improve chip scale package electrostatic discharge performance and suppress marking artifacts
12/17/2002	US6495379 Semiconductor device manufacturing method
12/17/2002	US6495270 Addition product of a heterocyclic amidine and a quinone is accelerator; encapsulation of electronic component parts; rapid curability, curability after moisture absorption under moist condition, pot life and flow properties
12/17/2002	US6495260 Grinding a mixture of epoxy resin and phenolic resin to form a powder, melt kneading; very few voids

1 ... 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 ... 2262