H01L 23 - Details of semiconductor or other solid state devices

Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
12/2002
12/10/2002	US6492729 Configuration and method for connecting conductor tracks
12/10/2002	US6492727 Semiconductor device
12/10/2002	US6492726 Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
12/10/2002	US6492725 Concentrically leaded power semiconductor device package
12/10/2002	US6492724 Structure for reinforcing a semiconductor device to prevent cracking
12/10/2002	US6492723 Multichip module
12/10/2002	US6492721 High-voltage signal detecting circuit
12/10/2002	US6492720 Flat-type semiconductor stack
12/10/2002	US6492719 Semiconductor device
12/10/2002	US6492718 Stacked semiconductor device and semiconductor system
12/10/2002	US6492717 Smart card module and method of assembling the same
12/10/2002	US6492716 Seal ring structure for IC containing integrated digital/RF/analog circuits and functions
12/10/2002	US6492715 Integrated semiconductor package
12/10/2002	US6492713 Gravitationally assisted control of spread of viscous material applied to semiconductor assembly components
12/10/2002	US6492707 Semiconductor integrated circuit device with pad impedance adjustment mechanism
12/10/2002	US6492705 Integrated circuit air bridge structures and methods of fabricating same
12/10/2002	US6492698 Flexible circuit with two stiffeners for optical module packaging
12/10/2002	US6492692 Semiconductor integrated circuit and manufacturing method therefore
12/10/2002	US6492683 Semiconductor device with SOI structure and method of manufacturing the same
12/10/2002	US6492674 Semiconductor device having an improved plug structure and method of manufacturing the same
12/10/2002	US6492667 Radio frequency semiconductor apparatus
12/10/2002	US6492666 Semiconductor wafer with scribe lines having inspection pads formed thereon
12/10/2002	US6492620 Equipotential fault tolerant integrated circuit heater
12/10/2002	US6492600 Laminate having plated microvia interconnects and method for forming the same
12/10/2002	US6492593 Gold wire for semiconductor element connection, used for electrical connection of external leads and the like to electrodes on semiconductor elements; suitable for narrow pitch connections and thin electrode connections
12/10/2002	US6492282 Integrated circuits and manufacturing methods
12/10/2002	US6492271 Semiconductor device and method of manufacturing the same
12/10/2002	US6492269 Methods for edge alignment mark protection during damascene electrochemical plating of copper
12/10/2002	US6492268 Method of forming a copper wiring in a semiconductor device
12/10/2002	US6492266 Method of forming reliable capped copper interconnects
12/10/2002	US6492262 Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies
12/10/2002	US6492259 Process for making a planar integrated circuit interconnect
12/10/2002	US6492258 METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-μM AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY
12/10/2002	US6492255 Semiconductor chip and method manufacturing the same
12/10/2002	US6492254 Ball grid array (BGA) to column grid array (CGA) conversion process
12/10/2002	US6492253 Method for programming a substrate for array-type packages
12/10/2002	US6492251 Microelectronic joining processes with bonding material application
12/10/2002	US6492247 Method for eliminating crack damage induced by delaminating gate conductor interfaces in integrated circuits
12/10/2002	US6492245 Method of forming air gap isolation between a bit line contact structure and a capacitor under bit line structure
12/10/2002	US6492219 High voltage shield
12/10/2002	US6492207 Method for making a pedestal fuse
12/10/2002	US6492206 Antifuse with improved radiation SEDR
12/10/2002	US6492205 Utilization of macro power routing area for buffer insertion
12/10/2002	US6492204 Electronic devices having thermodynamic encapsulant portions predominating over thermostatic encapsulant portions
12/10/2002	US6492203 Semiconductor device and method of fabrication thereof
12/10/2002	US6492202 Method of assembling components onto a circuit board
12/10/2002	US6492201 Forming microelectronic connection components by electrophoretic deposition
12/10/2002	US6492200 Semiconductor chip package and fabrication method thereof
12/10/2002	US6492199 Method of manufacturing a semiconductor package with improved cross talk and grounding
12/10/2002	US6492198 Method for fabricating a semiconductor device
12/10/2002	US6492196 Packaging process for wafer level IC device
12/10/2002	US6492195 Method of thinning a semiconductor substrate using a perforated support substrate
12/10/2002	US6492194 Method for the packaging of electronic components
12/10/2002	US6492189 Method of arranging exposed areas including a limited number of test element group (TEG) regions on a semiconductor wafer
12/10/2002	US6492008 Multilayer printed wiring board and electronic equipment
12/10/2002	US6491969 Disposable print head for ejecting controlled amounts of liquid (e.g. solder) at a high rate onto the suface (e.g. an integrated circuit); heating a metal hydride layer to generate hydrogen gas, the pressure from which ejects solder
12/10/2002	US6491862 Method for producing SiC preform with high volume fraction
12/10/2002	US6491757 Wafer support system
12/10/2002	US6490877 Multi-load refrigeration system with multiple parallel evaporators
12/10/2002	CA2261551C Socket for integrated circuit chip
12/05/2002	WO2002097890A2 Bitline contacts in a memory cell array
12/05/2002	WO2002097886A2 Semiconductor structure comprising an electrostatic discharge (esd) protection device
12/05/2002	WO2002097885A1 Contact system
12/05/2002	WO2002097883A1 High power semiconductor module
12/05/2002	WO2002097882A1 A heat dissipation device having a load centering mechanism
12/05/2002	WO2002097881A2 Folded-fin heat sink assembly and method of manufacturing same
12/05/2002	WO2002097880A2 Power semiconductor module and method for the production of a power semiconductor module
12/05/2002	WO2002097877A1 A method of packaging a semiconductor chip
12/05/2002	WO2002097868A2 Integrated circuit having an energy-absorbing structure
12/05/2002	WO2002097147A1 Metal-ceramic composite material
12/05/2002	WO2002096636A1 Interface materials and methods of production and use thereof
12/05/2002	WO2002069684A3 Pin grid array socket with reinforcement plate
12/05/2002	WO2002049105A3 Thermoelectric spot coolers for rf and microwave communication integrated circuits
12/05/2002	WO2002049101A3 Intermediate support for a semiconductor module and arrangement of a module which is configured with an intermediate support of this type on a circuit support
12/05/2002	WO2002047177A3 Enhanced interface thermoelectric coolers
12/05/2002	WO2002047176A3 Enhanced interface thermoelectric coolers
12/05/2002	WO2002047158A3 Ionized metal plasma deposition process having enhanced via sidewall coverage
12/05/2002	US20020184601 Method and apparatus for circuit design
12/05/2002	US20020184426 Method of terminating bus, bus termination resistor, and wiring substrate having terminated buses and method of its manufacture
12/05/2002	US20020183431 Comprises hygroscopic agent (calcium oxide, barium oxide, and/or strontium oxide) and polymer (fluoropolymers, polyacrylate, polyacrylonitrile, polyamide, polyester, or epoxy resin); for use in electronic parts (batteries)
12/05/2002	US20020183029 High frequency power amplifying apparatus having amplifying stages with gain control signals of lower amplitudes applied to earlier preceding stages
12/05/2002	US20020182916 IC socket
12/05/2002	US20020182903 Printed wiring board and manufacturing method therefor
12/05/2002	US20020182891 Method of forming dielectric film and dielectric film
12/05/2002	US20020182887 Method and apparatus of forming a sputtered doped seed layer
12/05/2002	US20020182872 Material removal method for forming a structure
12/05/2002	US20020182869 Method for forming dual-damascene interconnect structure
12/05/2002	US20020182862 Optimized TaCN thin film diffusion barrier for copper metallization
12/05/2002	US20020182859 Structures and methods to enhance copper metallization
12/05/2002	US20020182858 Forming insulator layer having substance, forming inhibiting layer on insulator layer, wherein forming inhibiting layer includes depositing second substance on insulator layer, forming a copper metallization layer on the inhibiting layer
12/05/2002	US20020182855 Dual damascene multi-level metallization
12/05/2002	US20020182853 Method for removing hard-mask layer after metal-CMP in dual-damascene interconnect structure
12/05/2002	US20020182848 Method of improving the fabrication of etched semiconductor devices
12/05/2002	US20020182847 Method of manufacturing semiconductor device
12/05/2002	US20020182846 Semiconductor devices having contact plugs and local interconnects and methods for making the same
12/05/2002	US20020182845 Method of filling a concave portion with an insulating material
12/05/2002	US20020182844 Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
12/05/2002	US20020182843 Method for connecting semiconductor unit to object via bump
12/05/2002	US20020182841 Compliant integrated circuit package
12/05/2002	US20020182838 Fuse in semiconductor device and fabricating method thereof

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