Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 23 - Details of semiconductor or other solid state devices
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
05/2003
05/27/2003US6570236 Semiconductor device
05/27/2003US6570233 Processing a bit line contact and a storage node contact used mainly in each element of a dynamic random access memory; reducing the direct contact resistance; and reducing the junction leak while maintaining the punch through margin
05/27/2003US6570232 Local interconnect structure for integrated circuit devices, source structure for the same, and method for fabricating the same
05/27/2003US6570231 Semiconductor device with varying width electrode
05/27/2003US6570207 Can be accessed directly without having to turn on a transfer gate.
05/27/2003US6570203 Semiconductor device and method of manufacturing the same
05/27/2003US6570199 Semiconductor device and method of manufacturing the same
05/27/2003US6570182 Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof
05/27/2003US6570181 Semiconductor metal interconnect reliability test structure
05/27/2003US6570102 Structure for high speed printed wiring boards with multiple differential impedance-controlled layer
05/27/2003US6570101 Lead configurations
05/27/2003US6570100 Pad structure of semiconductor package
05/27/2003US6570099 Thermal conductive substrate and the method for manufacturing the same
05/27/2003US6570029 No-flow reworkable epoxy underfills for flip-chip applications
05/27/2003US6569785 Semiconductor integrated circuit device having internal tensile and internal compression stress
05/27/2003US6569783 Graded composition diffusion barriers for chip wiring applications
05/27/2003US6569782 Insulating layer, semiconductor device and methods for fabricating the same
05/27/2003US6569768 Surface treatment and capping layer process for producing a copper interface in a semiconductor device
05/27/2003US6569767 Semiconductor device and its production process
05/27/2003US6569764 Method of manufacturing a semiconductor package by attaching a lead frame to a semiconductor chip via projecting electrodes and an insulating sheet of resin material
05/27/2003US6569759 Semiconductor device having interconnection implemented by refractory metal nitride layer and refractory metal silicide layer and process of fabrication thereof
05/27/2003US6569758 Sub-milliohm on-chip interconnection
05/27/2003US6569757 Methods for forming co-axial interconnect lines in a CMOS process for high speed applications
05/27/2003US6569756 Method for manufacturing a semiconductor device
05/27/2003US6569755 Semiconductor device having an improved structure for preventing cracks, improved small sized semiconductor and method of manufacturing the same
05/27/2003US6569752 Semiconductor element and fabricating method thereof
05/27/2003US6569746 Methods of forming integrated circuit capacitors having electrodes therein that comprise conductive plugs
05/27/2003US6569727 Method of making a single-deposition-layer-metal dynamic random access memory
05/27/2003US6569712 Structure of a ball-grid array package substrate and processes for producing thereof
05/27/2003US6569711 Methods and apparatus for balancing differences in thermal expansion in electronic packaging
05/27/2003US6569710 Panel structure with plurality of chip compartments for providing high volume of chip modules
05/27/2003US6569708 Repairable flip chip semiconductor device with excellent packaging reliability and method of manufacturing same
05/27/2003US6569694 Method of checking BGA substrate design
05/27/2003US6569604 Blind via formation in a photoimageable dielectric material
05/27/2003US6569532 With porous silica inorganic filler and curing agent; readily moldable, low moisture permeability and reliability in the cured state
05/27/2003US6569524 High thermal conductivity composite material, and method for producing the same
05/27/2003US6569518 Nanotechnology for electrochemical and energy devices
05/27/2003US6569514 Ceramic circuit board and method of manufacturing the same
05/27/2003US6569490 Nanotechnology for chemical radiation, and biotechnology sensors
05/27/2003US6569380 Combined enclosure and heat sink formed without an adhesive layer
05/27/2003US6569033 Striking plate for a golf club head
05/27/2003US6568863 Disposing an optical fiber, sealing the optical fiber and the interconnecting line with a molding material, and removing the interconnecting line, the molding material together with the optical fiber from the mold
05/27/2003US6568464 Heat sink clip assembly
05/22/2003WO2003043397A1 Electronic apparatus
05/22/2003WO2003043094A1 Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion
05/22/2003WO2003043085A2 Electronic device carrier adapted for transmitting high frequency signals
05/22/2003WO2003043084A2 Semiconductor package having multi-signal bus bars
05/22/2003WO2003043083A1 Controlled impedance transmission lines in a redistribution layer
05/22/2003WO2003043082A1 Package for electronic parts, lid thereof, material for the lid and method for producing the lid material
05/22/2003WO2003043081A2 An electronic assembly having a wetting layer on a thermally conductive heat spreader
05/22/2003WO2003043074A2 Semiconductor component and method for contacting said semiconductor component
05/22/2003WO2003043064A1 Substrate inspecting device, coating/developing device and substrate inspecting method
05/22/2003WO2003043044A1 Mems device having a trilayered beam and related methods
05/22/2003WO2003043042A1 Mems device having electrothermal actuation and release and method for fabricating
05/22/2003WO2003043038A2 Mems device having contact and standoff bumps and related methods
05/22/2003WO2003042741A2 Multilayer monolithic electronic device and method for making same
05/22/2003WO2003042721A2 Trilayered beam mems device and related methods
05/22/2003WO2003023289A3 Integrated cooler for electronic devices
05/22/2003WO2003019651A3 Through-via vertical interconnects, through-via heat sinks and associated fabrication methods
05/22/2003WO2003012867A3 Emi shielding for electronic packages
05/22/2003WO2003003457A3 Design of lithography alignment and overlay measurement marks on damascene surface
05/22/2003WO2002069404A3 Circuit arrangement
05/22/2003WO2002059968B1 Integrated circuits protected against reverse engineering using an apparent metal contact line terminating on field oxide and method
05/22/2003WO2002056912A3 Pharmaceutical combination for the treatment of cancer containing a 4-quinazolineamine and another anti-neoplastic agent
05/22/2003WO2002043456A3 Interference mitigation through conductive thermoplastic composite materials
05/22/2003WO2001000137A3 Apparatus and method for setting the parameters of an alert window used for timing the delivery of etc signals to a heart under varying cardiac conditions
05/22/2003WO2000048444A3 Packaging for a semiconductor chip
05/22/2003US20030097641 Method of designing semiconductor device and semiconductor device
05/22/2003US20030096585 Radiocommunications device including a heat dissipation system
05/22/2003US20030096524 Retention mechanism for an electrical assembly
05/22/2003US20030096497 Electrode structure for use in an integrated circuit
05/22/2003US20030096495 Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device
05/22/2003US20030096494 Method of making semiconductor device
05/22/2003US20030096493 Perimeter anchored thick film pad
05/22/2003US20030096491 Method for fabricating a semiconductor device having a metallic silicide layer
05/22/2003US20030096488 Method and semiconductor wafer configuration for producing an alignment mark for semiconductor wafers
05/22/2003US20030096487 Method of forming an integrated inductor and high speed interconnect in a planarized process with shallow trench isolation
05/22/2003US20030096461 Integrated circuit resistant to the formation of cracks in a passivation layer
05/22/2003US20030096456 Semiconductor devices having their exposed edges defined by cutting apart two of the semiconductor preassembly; then moving the first semiconductor device against another element to break loose flash on the first exposed edge; appearance
05/22/2003US20030096455 Method of manufacturing semiconductor device having tie bars for interconnecting leads
05/22/2003US20030096454 Stackable semiconductor package and wafer level fabrication method
05/22/2003US20030096450 Power device and direct aluminum bonded substrate thereof
05/22/2003US20030096449 Chip scale package provided with a stress relieving layer having a sloping edge and specific size wiring over it from the electrodes; allows the ommission of a patterned flexible substrate and many components to be made simultaneously
05/22/2003US20030096447 Single and multiple layer packaging of high-speed/high-density ICs
05/22/2003US20030096436 Test structures and methods for inspection of semiconductor integrated circuits
05/22/2003US20030096116 Heat dissipating structure
05/22/2003US20030096059 Semiconductors; void occurence suppressed in junction layer; occurrence of cracks, swelling, and exfoliation in the plating layer suppressed
05/22/2003US20030095451 Laser link structure capable of preventing an upper crack and broadening an energy window of a laser beam, and fuse box using the same
05/22/2003US20030095429 Semiconductor memory device
05/22/2003US20030095393 Wireless bonded semiconductor device and method for packaging the same
05/22/2003US20030095014 Connection package for high-speed integrated circuit
05/22/2003US20030094996 Integrated circuit having a programmable element and method of operating the circuit
05/22/2003US20030094969 Semiconductor device
05/22/2003US20030094963 Device for testing electrical characteristics of chips
05/22/2003US20030094958 Pseudo variable resistor for tester platform
05/22/2003US20030094707 Method of ball grid array (BGA) alignment, method of testing, alignment apparatus and semiconductor device assembly
05/22/2003US20030094706 Method of ball grid array (BGA) alignment, method of testing, alignment apparatus and semiconductor device assembly
05/22/2003US20030094705 Semiconductor device and method of manufacturing the same
05/22/2003US20030094704 Method of fabricating known good dies from packaged integrated circuits
05/22/2003US20030094703 Integrated circuit bonding device and manufacturing method thereof
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