Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 23 - Details of semiconductor or other solid state devices
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
06/2003
06/18/2003CN1111906C Plastic-encapsulated semiconductor device and fabrication method thereof
06/18/2003CN1111902C Semiconductor device with aluminum containing interconnected wires
06/17/2003US6581201 Method for power routing and distribution in an integrated circuit with multiple interconnect layers
06/17/2003US6581195 Method and apparatus for extracting parasitic element of semiconductor circuit
06/17/2003US6580957 Method of efficiently laser marking singulated semiconductor devices
06/17/2003US6580620 Matrix type printed circuit board for semiconductor packages
06/17/2003US6580619 Multilayer reference plane in package devices
06/17/2003US6580618 Low-profile multi-chip module
06/17/2003US6580613 Solder-free PCB assembly
06/17/2003US6580612 Electric circuit
06/17/2003US6580610 Integrated EMI containment and spray cooling module utilizing a magnetically coupled pump
06/17/2003US6580609 Method and apparatus for cooling electronic components
06/17/2003US6580608 Method and apparatus for thermally controlling multiple electronic components
06/17/2003US6580595 Predetermined symmetrically balanced amalgam with complementary paired portions comprising shielding electrodes and shielded electrodes and other predetermined element portions for symmetrically balanced and complementary energy portion conditioning
06/17/2003US6580403 Housing for an electronic component
06/17/2003US6580395 High-frequency communication apparatus and method of manufacturing the same
06/17/2003US6580369 Electronic tag assembly and method therefor
06/17/2003US6580316 Power transistor module, power amplifier and methods in the fabrication thereof
06/17/2003US6580184 Electrostatic discharge (ESD) protection circuit of silicon-controlled rectifier (SCR) structure operable at a low trigger voltage
06/17/2003US6580176 No grain boundary is contained in region of wiring between upper and lower plugs; difference in thermal expansion coefficient between material of wiring and material of upper and lower plugs is so small that no void is generated
06/17/2003US6580175 Semiconductor layout structure for a conductive layer and contact hole
06/17/2003US6580173 Semiconductor device and manufacturing method of semiconductor device
06/17/2003US6580171 Semiconductor wiring device
06/17/2003US6580170 Semiconductor device protective overcoat with enhanced adhesion to polymeric materials
06/17/2003US6580169 Method for forming bumps, semiconductor device, and solder paste
06/17/2003US6580168 Method for manufacturing a low-profile semiconductor device
06/17/2003US6580167 Heat spreader with spring IC package
06/17/2003US6580166 High frequency semiconductor device
06/17/2003US6580165 Flip chip with solder pre-plated leadframe including locating holes
06/17/2003US6580164 Semiconductor device and method of manufacturing same
06/17/2003US6580163 IC chip packaging for reducing bond wire length
06/17/2003US6580162 Ball grid array (BGA) semiconductor package improving solder joint reliability
06/17/2003US6580161 Semiconductor device and method of making the same
06/17/2003US6580160 Coupling spaced bond pads to a contact
06/17/2003US6580159 Integrated circuit device packages and substrates for making the packages
06/17/2003US6580158 High speed IC package configuration
06/17/2003US6580157 Assembly and method for modified bus bar with Kapton™ tape or insulative material in LOC packaged part
06/17/2003US6580156 Integrated fuse with regions of different doping within the fuse neck
06/17/2003US6580155 Semiconductor device
06/17/2003US6580153 Structure for protecting a micromachine with a cavity in a UV tape
06/17/2003US6580152 Semiconductor with plural side faces
06/17/2003US6580145 Low programming voltage anti-fuse structure
06/17/2003US6580144 One time programmable fuse/anti-fuse combination based memory cell
06/17/2003US6580143 Thin-film circuit substrate and method of producing same
06/17/2003US6580142 Electrical control methods involving semiconductor components
06/17/2003US6580126 Solid-state relay
06/17/2003US6580092 Semiconductor chip, semiconductor device, and process for producing a semiconductor device
06/17/2003US6580036 Multi-layer printed circuit board and a BGA semiconductor package using the multi-layer printed circuit board
06/17/2003US6580031 Method for making a flexible circuit interposer having high-aspect ratio conductors
06/17/2003US6579806 Method of etching tungsten or tungsten nitride in semiconductor structures
06/17/2003US6579804 Contact structure and production method thereof and probe contact assembly using same
06/17/2003US6579794 Tungsten layer formation method for semiconductor device and semiconductor device using the same
06/17/2003US6579789 Method for fabricating metal wiring and the metal wiring
06/17/2003US6579787 Semiconductor device with a fluorinated silicate glass film as an interlayer metal dielectric film, and manufacturing method thereof
06/17/2003US6579785 Method of making multi-level wiring in a semiconductor device
06/17/2003US6579776 Method of manufacturing semiconductor device
06/17/2003US6579748 Fabrication method of an electronic component
06/17/2003US6579747 Method of making electronics package with specific areas having low coefficient of thermal expansion
06/17/2003US6579746 Method and apparatus for coupling a semiconductor die to die terminals
06/17/2003US6579743 Chip packaging system and method using deposited diamond film
06/17/2003US6579738 Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials
06/17/2003US6579734 Wire bonding method
06/17/2003US6579666 Methodology to introduce metal and via openings
06/17/2003US6579623 Composite material member for semiconductor device and insulated and non-insulated semiconductor devices using composite material member
06/17/2003US6579474 A conductive composition, and articles and methods using the conductive composition are disclosed. conductive particles in an amount of at least about 75 wt. % based on the weight of the composition, wherein at least 50% by weight of the
06/17/2003US6579106 Electrical connecting structure of a tape carrier package for a LCD driver
06/17/2003US6578755 Polymer collar for solder bumps
06/17/2003US6578754 Pillar connections for semiconductor chips and method of manufacture
06/17/2003US6578626 Liquid cooled heat exchanger with enhanced flow
06/17/2003US6578625 Method and apparatus for removing heat from a plate
06/17/2003US6578458 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions
06/17/2003US6578262 Heat transfer material for an improved die edge contacting socket
06/13/2003CA2413369A1 Electronic module including a low temperature co-fired ceramic (ltcc) substrate with a capacitive structure embedded therein and related methods
06/12/2003WO2003049512A1 Ball grid array package
06/12/2003WO2003049185A2 Semiconductor component circuit with a reduced oscillation tendency
06/12/2003WO2003049184A1 Semiconductor device and method for manufacturing the same
06/12/2003WO2003049183A2 Optimum power and ground bump pad and bump patterns for flip chip packaging
06/12/2003WO2003049178A2 Semiconductor power device metal structure and method of formation
06/12/2003WO2003049174A1 Methods and apparatus for providing improved physical designs and routing with reduced capacitive power dissipation
06/12/2003WO2003049161A1 Interconnects with improved barrier layer adhesion
06/12/2003WO2003049158A1 Arrangement comprising a capacitor
06/12/2003WO2003049155A1 System and method for laser micro- machining
06/12/2003WO2003049152A2 Backside metallization on sides of microelectronic dice for effective thermal contact with heat dissipation devices
06/12/2003WO2003049149A2 Apparatus and method for inter-chip or chip-to-substrate connection with a sub-carrier
06/12/2003WO2003049147A2 Integrated circuits including metal oxide and hydrogen barrier layers and their method of fabrication
06/12/2003WO2003048981A2 Improving integrated circuit performance and reliability using a patterned bump layout on a power grid
06/12/2003WO2003048407A1 Gcib processing to improve interconnection vias and improved interconnection via
06/12/2003WO2003025998A3 Method of forming a bond pad and structure thereof
06/12/2003WO2002089538A3 Finned heat sink assemblies
06/12/2003WO2002059944A8 Optimized liners for dual damascene metal wiring
06/12/2003US20030110452 Electronic package design with improved power delivery performance
06/12/2003US20030109183 Process for bonding and electrically connecting microsystems integrated in several distinct substrates
06/12/2003US20030109163 Socket for electrical parts
06/12/2003US20030109141 Wafer scribing method and wafer scribing device
06/12/2003US20030109136 Semiconductor device and method of manufacturing the same
06/12/2003US20030109134 Method of manufacturing semiconductor device and method of determining film formation time, chamber, chemical vapor deposition apparatus and boat thereof, etching apparatus, and film formation process system
06/12/2003US20030109133 Process for fabricating an electronic component incorporating an inductive microcomponent
06/12/2003US20030109129 Semiconductor device
06/12/2003US20030109128 Semiconductor device and method of manufacturing the same
06/12/2003US20030109125 Fuse structure for a semiconductor device and manufacturing method thereof
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