Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
07/2003
07/23/2003CN2562423Y Electric connector fetch devices
07/23/2003CN2562369Y Elastic electric contacts packing structure
07/23/2003CN2562368Y Liquid cooling radiator
07/23/2003CN2562367Y Improved radiator combining structure
07/23/2003CN2562366Y Radiator assembly
07/23/2003CN2562365Y 散热器 Heat sink
07/23/2003CN2562364Y Semiconductor package shell and installation structure
07/23/2003CN2562230Y Radiators
07/23/2003CN2562229Y Radiator rib device of radiator
07/23/2003CN2562228Y Multiline positioning buckle for CPU radiator
07/23/2003CN2562225Y Radiator element
07/23/2003CN2562224Y Rotary central microprocessor cooler
07/23/2003CN1432195A Semiconductor component comprising surface metallization
07/23/2003CN1432193A Method and device for fleed out control in solder bonding
07/23/2003CN1432074A Electrolyte and method for depositing tin-silver alloy layers
07/23/2003CN1432048A Polymer resin for ion beam or ion injection treatment to give surface conductiveness
07/23/2003CN1432040A Epoxy-resin systems, which are resistant to ageing, moulding materials and components produced therefrom and use thereof
07/23/2003CN1431979A Material composite and prodn. and use of material composite
07/23/2003CN1431858A Printed circuit board with built-in passive device, its mfg. method and used substrate
07/23/2003CN1431710A 半导体装置 Semiconductor device
07/23/2003CN1431709A 电子器件 Electronic devices
07/23/2003CN1431708A Wafer formed diffusion type capsulation structure and its mfg. methods
07/23/2003CN1431707A Heat dispersion modules and their mfg. methods
07/23/2003CN1431706A Method for mfg. contact type modules with moulded package
07/23/2003CN1431703A Method for lowering anomaly discharges happened on interconnected wires in plasma procedure
07/23/2003CN1431681A Method for encapsulation in chip level by use of electroplating mask of elastic body
07/23/2003CN1431573A Computer cooling device
07/23/2003CN1115725C Process for forming multilevel interconnection structure
07/23/2003CN1115721C Semiconductor device testing appts.
07/23/2003CN1115719C Alignment method
07/23/2003CN1115243C Thermal conducting interface
07/22/2003US6598217 Method of mounting fabrication-historical data for semiconductor device, and semiconductor device fabricated by such a method
07/22/2003US6598206 Method and system of modifying integrated circuit power rails
07/22/2003US6597952 Apparatus and method for setting the parameters of an alert window used for timing the delivery of ETC signals to a heart under varying cardiac conditions
07/22/2003US6597902 Radio-frequency circuit module
07/22/2003US6597805 Visual inspection method for electronic device, visual inspecting apparatus for electronic device, and record medium for recording program which causes computer to perform visual inspecting method for electronic device
07/22/2003US6597583 Multilayer circuit board having a capacitor and process for manufacturing same
07/22/2003US6597582 Semiconductor device incorporating module structure
07/22/2003US6597575 Heat exchangers for integrated circuit pakaging comprising silicone oils and fillers as thermoconductive interfaces
07/22/2003US6597574 Radiator plate and process for manufacturing the same
07/22/2003US6597562 Electrically polar integrated capacitor and method of making same
07/22/2003US6597234 Anti-fuse circuit and method of operation
07/22/2003US6597227 System for providing electrostatic discharge protection for high-speed integrated circuits
07/22/2003US6597187 Special contact points for accessing internal circuitry of an integrated circuit
07/22/2003US6597182 Detector for detecting contact resistance anomaly of cathode electrode in electroplating machine
07/22/2003US6597070 Semiconductor device and method of manufacturing the same
07/22/2003US6597069 Flip chip metallization
07/22/2003US6597068 Encapsulated metal structures for semiconductor devices and MIM capacitors including the same
07/22/2003US6597067 Self-aligned, lateral diffusion barrier in metal lines to eliminate electromigration
07/22/2003US6597066 Hermetic chip and method of manufacture
07/22/2003US6597065 Thermally enhanced semiconductor chip having integrated bonds over active circuits
07/22/2003US6597063 Package for semiconductor power device and method for assembling the same
07/22/2003US6597060 Semiconductor device package
07/22/2003US6597059 Thermally enhanced chip scale lead on chip semiconductor package
07/22/2003US6597058 Method of forming defect-free ceramic structures using thermally depolymerizable surface layer
07/22/2003US6597055 Redundancy structure in self-aligned contacts
07/22/2003US6597054 Reduced pitch laser redundancy fuse bank structure
07/22/2003US6597053 Integrated circuit arrangement with a number of structural elements and method for the production thereof
07/22/2003US6597049 Conductor structure for a magnetic memory
07/22/2003US6597045 Semiconductor raised source-drain structure
07/22/2003US6597042 Contact with germanium layer
07/22/2003US6597020 Process for packaging a chip with sensors and semiconductor package containing such a chip
07/22/2003US6597019 Semiconductor light-emitting device comprising an electrostatic protection element
07/22/2003US6597013 Low current blow trim fuse
07/22/2003US6596964 Method of attaching a component to a connection support by welding without the addition of material
07/22/2003US6596937 Board-level conformal EMI shield having an electrically-conductive polymer coating over a thermally-conductive dielectric coating
07/22/2003US6596834 Silicone resins having the general formula (R1SiO3/2)x(HSiO3/2)y where R1 is an alkyl group having 8 to 24 carbon atoms; x has a value of 0.05 to 0.7; y has a value of 0.3 to 0.95 and x+y =1. The resins are used to form porous
07/22/2003US6596813 Composition of epoxy resin, phenolic resin, butadiene particles and amino silicone oil
07/22/2003US6596648 Material removal method for forming a structure
07/22/2003US6596642 Material removal method for forming a structure
07/22/2003US6596640 Method of forming a raised contact for a substrate
07/22/2003US6596635 Method for metallization of a semiconductor substrate
07/22/2003US6596634 Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument
07/22/2003US6596633 Method for manufacturing a semiconductor device
07/22/2003US6596632 Method for forming an integrated circuit interconnect using a dual poly process
07/22/2003US6596631 Method of forming copper interconnect capping layers with improved interface and adhesion
07/22/2003US6596629 Method for forming wire in semiconductor device
07/22/2003US6596628 Electrode pad in semiconductor device and method of producing the same
07/22/2003US6596627 Very low dielectric constant plasma-enhanced CVD films
07/22/2003US6596624 Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a chip carrier
07/22/2003US6596622 Semiconductor device having a multi-layer pad and manufacturing method thereof
07/22/2003US6596621 Method of forming a lead-free tin-silver-copper based solder alloy on an electronic substrate
07/22/2003US6596620 BGA substrate via structure
07/22/2003US6596619 Method for fabricating an under bump metallization structure
07/22/2003US6596611 Method for forming wafer level package having serpentine-shaped electrode along scribe line and package formed
07/22/2003US6596610 Method for reclaiming delaminated wafer and reclaimed delaminated wafer
07/22/2003US6596606 Semiconductor raised source-drain structure
07/22/2003US6596604 Method of preventing shift of alignment marks during rapid thermal processing
07/22/2003US6596603 Semiconductor device and manufacturing method thereof, and registration accuracy measurement enhancement method
07/22/2003US6596592 Structures and methods of anti-fuse formation in SOI
07/22/2003US6596589 Method of manufacturing a high coupling ratio stacked gate flash memory with an HSG-SI layer
07/22/2003US6596581 Method for manufacturing a semiconductor device having a metal-insulator-metal capacitor and a damascene wiring layer structure
07/22/2003US6596579 Method of forming analog capacitor dual damascene process
07/22/2003US6596578 Semiconductor device and manufacturing method thereof
07/22/2003US6596566 Conformal-coated pick and place compatible devices
07/22/2003US6596565 Chip on board and heat sink attachment methods
07/22/2003US6596564 Semiconductor device and method of manufacturing the same
07/22/2003US6596563 Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug
07/22/2003US6596561 Method of manufacturing a semiconductor device using reinforcing patterns for ensuring mechanical strength during manufacture
07/22/2003US6596560 Method of making wafer level packaging and chip structure