Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
08/2003
08/12/2003US6605530 Method for fabricating semiconductor integrated circuit
08/12/2003US6605528 Post passivation metal scheme for high-performance integrated circuit devices
08/12/2003US6605526 Wirebond passivation pad connection using heated capillary
08/12/2003US6605525 Stress buffer layer
08/12/2003US6605523 Manufacturing method for semiconductor device
08/12/2003US6605522 Method of manufacturing a semiconductor device having a protruding bump electrode
08/12/2003US6605516 Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns
08/12/2003US6605492 Plastic ball grid array assembly
08/12/2003US6605490 Semiconductor device and production process thereof
08/12/2003US6605489 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
08/12/2003US6605480 Wafer level packaging for making flip-chips
08/12/2003US6605355 Semiconductor connections
08/12/2003US6605331 Asymmetric transfer molding method and an asymmetric encapsulation made therefrom
08/12/2003US6605238 Vinyl alcohol modified polydimethylsilanol, dimethyl silandiol-methylsilandiol copolymer, a dimethylvinylsilanol modified polysilicate, a platinum vinylsiloxane, a wetting agent and a thermoconductive filler; enhance heat dissipation
08/12/2003US6604671 Bondhead lead clamp apparatus and method
08/12/2003US6604370 Variably configured sprayjet cooling system
08/12/2003US6604276 Method for fabricating a chip-type varistor having a glass coating layer
08/12/2003CA2162189C Insulator for integrated circuits and process
08/12/2003CA2115659C Pyroelectric sensor and fabrication process
08/07/2003WO2003065779A1 Method for embedding a component in a base
08/07/2003WO2003065778A1 Method for embedding a component in a base and forming a contact
08/07/2003WO2003065775A2 Heat-sink with large fins-to-air contact area
08/07/2003WO2003065630A2 Apparatus and method for preventing digital media piracy
08/07/2003WO2003065487A1 Semiconductor device having fuel cell and its manufacturing method
08/07/2003WO2003065473A1 Electronic devices containing organic semiconductor materials
08/07/2003WO2003065469A2 Power module
08/07/2003WO2003065454A2 Split-gate power module and method for suppressing oscillation therein
08/07/2003WO2003065453A1 Receptacle for a programmable, electronic processing device
08/07/2003WO2003065452A1 A lead frame
08/07/2003WO2003065451A1 Flip chip die bond pads, die bond pad placement and routing optimization
08/07/2003WO2003065450A2 Integrated circuits with backside contacts and methods for their fabrication
08/07/2003WO2003065449A2 Power semiconductor, and method for producing the same
08/07/2003WO2003065448A1 Chip-size package with an integrated passive component
08/07/2003WO2003065447A2 No-flow underfill encapsulant
08/07/2003WO2003065446A1 Multi-layer ceramic substrate, and method and device for producing the same
08/07/2003WO2003065445A1 Method for preparing gas-tight terminal
08/07/2003WO2003064713A1 Thermal interface materials; and compositions comprising indium and zinc
08/07/2003WO2003064506A1 High adhesive liquid crystalline polymer film
08/07/2003WO2003064493A1 No flow underfill composition
08/07/2003WO2003064148A1 Thermal interface materials
08/07/2003WO2003027690A9 Test structures for estimating dishing and erosion effects in copper damascene technology
08/07/2003WO2003026006A3 Arrangement of a semiconductor in a housing, chip card and chip module
08/07/2003WO2003019649A3 Strip conductor arrangement and method for producing a strip conductor arrangement
08/07/2003WO2003009380A3 Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates
08/07/2003WO2002089205A3 Relay connector for an electronic component and a method for producing the same
08/07/2003WO2002082536A3 Laminated heat transfer device and method of producing thereof
08/07/2003WO2002061802A9 Metal-to-metal antifuse structure and fabrication method
08/07/2003WO2002059970A3 Mos transistor
08/07/2003WO2002050888A3 Method for making electronic devices including silicon and ltcc
08/07/2003WO2002047162A3 Microelectronic package having an integrated heat sink and build-up layers
08/07/2003WO2002015267A3 Integrated circuit package including opening exposing portion of an ic
08/07/2003US20030149942 Voltage reference circuit layout inside multi-layered substrate
08/07/2003US20030149159 Polymer composition containing clean filler incorporated therein
08/07/2003US20030149135 No-flow underfill encapsulant
08/07/2003US20030148739 High-frequency module device
08/07/2003US20030148613 Wireless communications system and method of making
08/07/2003US20030148604 Chip structure and process for forming the same
08/07/2003US20030148603 Novel interconnection structures and methods of fabrication
08/07/2003US20030148599 Method for bumped die and wire bonded board-on-chip package
08/07/2003US20030148598 Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications
08/07/2003US20030148597 Stacked die in die BGA package
08/07/2003US20030148596 Wafer bonding for three-dimensional (3D) integration
08/07/2003US20030148590 Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
08/07/2003US20030148579 Semiconductor device and method of manufacturing the same
08/07/2003US20030148578 Method and apparatus for building up large scale on chip de-coupling capacitor on standard CMOS/SOI technology
08/07/2003US20030148558 Integrated circuit and method of manufacturing thereof
08/07/2003US20030148557 BOC BGA package for die with I-shaped bond pad layout
08/07/2003US20030148556 Method and system for exposed die molding for integrated circuit packaging
08/07/2003US20030148554 Packaged semiconductor device and method of formation
08/07/2003US20030148552 Semiconductor structures with cavities, and methods of fabrication
08/07/2003US20030148108 Wafer interposer assembly and system for building same
08/07/2003US20030148079 Thermal conductive substrate and the method for manufacturing the same
08/07/2003US20030148077 High-performance laminate for integrated circuit interconnection
08/07/2003US20030148070 Carrier plate for micro-hybrid circuits
08/07/2003US20030147580 Packaging optically coupled integrated circuits using flip-chip methods
08/07/2003US20030147227 Multi-layered interconnect structure using liquid crystalline polymer dielectric
08/07/2003US20030147225 System including power conditioning modules
08/07/2003US20030147215 Package with high heat dissipation
08/07/2003US20030147213 Device for cooling CPU chip
08/07/2003US20030147204 Electronic circuit board case
08/07/2003US20030147190 Substrate-triggered bipolar junction transistor and ESD protection circuit
08/07/2003US20030147189 Signal shielding technique using active shields for non-interacting driver design
08/07/2003US20030147020 Liquid crystal display units
08/07/2003US20030146771 Wireless radio frequency technique design and method for testing of integrated circuits and wafers
08/07/2003US20030146520 Flip-chip package with a heat spreader
08/07/2003US20030146518 Semiconductor device of chip-on-chip structure, assembling process therefor, and semiconductor chip to be bonded to solid surface
08/07/2003US20030146517 Wires on electroconductive substrate; supplying voltage
08/07/2003US20030146516 Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method
08/07/2003US20030146515 Semiconductor device having wiring line with hole, and manufacturing method thereof
08/07/2003US20030146514 Semiconductor device and method of fabricating the same
08/07/2003US20030146513 Capacitance reduction by tunnel formation for use with semiconductor device
08/07/2003US20030146511 Ball grid array package with multiple interposers
08/07/2003US20030146510 Elastomer interposer for grid array packages and method of manufacturing the same
08/07/2003US20030146509 Ball grid array package with separated stiffener layer
08/07/2003US20030146508 Cavity-down ball grid array package with semiconductor chip solder ball
08/07/2003US20030146507 Thermally-enhanced ball grid array package structure and method
08/07/2003US20030146506 Ball grid array package fabrication with IC die support structures
08/07/2003US20030146505 Sperical core of high melting metal; connector of low melting eutectic
08/07/2003US20030146504 Chip-size semiconductor package
08/07/2003US20030146503 Ball grid array package with stepped stiffener layer