Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 23 - Details of semiconductor or other solid state devices
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
02/2005
02/10/2005WO2005013357A1 Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits
02/10/2005WO2005013356A1 Semiconductor device having trench wiring and process for fabricating semiconductor device
02/10/2005WO2005013353A2 Method for producing reduced-thickness electronic components
02/10/2005WO2005013352A2 Method for the production of a semiconductor element with a plastic housing and support plate for carrying out said method
02/10/2005WO2005013339A2 Methods of forming conductive structures including titanium-tungsten base layers and related structures
02/10/2005WO2005013330A2 Crack stop for low k dielectrics
02/10/2005WO2005013319A2 Semiconductor device with strain relieving bump design
02/10/2005WO2005013282A1 Wordline latching in semiconductor memories
02/10/2005WO2005012386A1 Epoxy resin composition for sealing and electronic part device
02/10/2005WO2004100261A3 Semiconductor wafer, panel and electronic component comprising stacked semiconductor chips, and method for the production thereof
02/10/2005WO2004095575A3 Electronic assembly with fluid cooling and associated methods
02/10/2005WO2004092829A3 Masking arrangement and method for producing integrated circuit arrangements
02/10/2005WO2004090941A3 Integrated circuit die having a copper contact and method therefor
02/10/2005WO2004075370A3 Minimum-dimension, fully-silicided mos driver and esd protection design for optimized inter-finger coupling
02/10/2005WO2004075294A3 Flip-chip component packaging process and flip-chip component
02/10/2005WO2004075221A3 Micro fuse
02/10/2005WO2004070792A3 Thin multiple semiconductor die package
02/10/2005US20050034093 Semiconductor integrated circuit device and method for designing the same
02/10/2005US20050032403 Structure for mounting electronic component
02/10/2005US20050032395 Methods for forming porous insulator structures on semiconductor devices
02/10/2005US20050032389 Method for avoiding erosion of DRAM fuse sidewall
02/10/2005US20050032387 Asymmetric plating
02/10/2005US20050032358 Semiconductor device and method for fabricating the same
02/10/2005US20050032356 Semiconductor device and method of manufacturing the same
02/10/2005US20050032353 Method for reducing defects in post passivation interconnect process
02/10/2005US20050032351 Chip structure and process for forming the same
02/10/2005US20050032349 Low fabrication cost, fine pitch and high reliability solder bump
02/10/2005US20050032348 Method of wafer bumping for enabling a stitch wire bond in the absence of discrete bump formation
02/10/2005US20050032347 Method for contacting electrical contact surfaces of a substrate and device consisting of a substrate having electrical contact surfaces
02/10/2005US20050032333 Wafer thinning using magnetic mirror plasma
02/10/2005US20050032320 Method for manufacturing a semiconductor device and a semiconductor device manufactured thereby
02/10/2005US20050032315 Semiconductor device and method of manufacturing the same
02/10/2005US20050032294 Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
02/10/2005US20050032293 Use of, silyating agents
02/10/2005US20050032285 Electronic device and defect repair method thereof
02/10/2005US20050032279 Antifuse structures, methods, and applications
02/10/2005US20050032273 Structure and method for fine pitch flip chip substrate
02/10/2005US20050032271 Lead frame, semiconductor device using the same and method of producing the semiconductor device
02/10/2005US20050032270 Methods for securing components of semiconductor device assemblies to each other with hybrid adhesive materials
02/10/2005US20050032267 RFID device and method of making
02/10/2005US20050032264 Method of manufacturing a semiconductor device
02/10/2005US20050032256 Semiconductor device with porous interlayer insulating film
02/10/2005US20050032253 Via array monitor and method of monitoring induced electrical charging
02/10/2005US20050032251 Method for manufacturing semiconductor devices by monitoring nitrogen bearing species in gate oxide layer
02/10/2005US20050032229 Probe tip design applied in a flip chip packaging process
02/10/2005US20050031995 Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same
02/10/2005US20050031889 iron layer and nickel layer having an iron-nickel layer between formed by heat treatment diffusion; relatively large thermal conductivity in a direction of thickness thereof
02/10/2005US20050031784 Barrier layer for electroplating processes
02/10/2005US20050030823 Electronic circuit device
02/10/2005US20050030821 Magnetic memory apparatus and method of manufacturing magnetic memory apparatus
02/10/2005US20050030815 Semiconductor memory module
02/10/2005US20050030762 Light-emitting diode lamp
02/10/2005US20050030718 Processor retention system and method
02/10/2005US20050030717 Cooler for cooling electric part
02/10/2005US20050030713 Cooling fan
02/10/2005US20050030700 Capacitor element, semiconductor integrated circuit and method of manufacturing those
02/10/2005US20050030699 Shielded capacitor structure
02/10/2005US20050030698 Electronic unit integrated into a flexible polymer body
02/10/2005US20050030688 ESD protection circuit having a control circuit
02/10/2005US20050030686 Integrated circuit having a plurality of output drivers
02/10/2005US20050030502 Photomask, exposure control method and method of manufacturing a semiconductor device
02/10/2005US20050030465 Contact structure of conductive films and thin film transistor array panel including the same
02/10/2005US20050030440 Thin film transistor array panel and manufacturing method thereof
02/10/2005US20050030231 High frequency circuit module
02/10/2005US20050030108 Integrated VCO having an improved tuning range over process and temperature variations
02/10/2005US20050030107 Semiconductor device
02/10/2005US20050030057 Semiconductor test device using leakage current and compensation system of leakage current
02/10/2005US20050029679 Semiconductor device and wire bonding apparatus
02/10/2005US20050029678 Growth of single crystal nanowires
02/10/2005US20050029677 [under bump metallurgic layer]
02/10/2005US20050029676 Solder masks including dams for at least partially surrounding terminals of a carrier substrate and recessed areas positioned adjacent to the dams, and carrier substrates including such solder masks
02/10/2005US20050029675 Tin/indium lead-free solders for low stress chip attachment
02/10/2005US20050029674 Multi-chip module
02/10/2005US20050029673 Multi-chip semiconductor device with specific chip arrangement
02/10/2005US20050029672 Flip chip package structure
02/10/2005US20050029671 Semiconductor device with copper wirings
02/10/2005US20050029669 Semiconductor device and method for manufacturing the same
02/10/2005US20050029668 Apparatus and method for packaging circuits
02/10/2005US20050029667 Electroconductive alloy of tin and lead; first fluxing agent reacting with oxide of metal to promote melting of metal at first temperature; second fluxing agent having higher melting temperature; resolidification; rosin or resin binder
02/10/2005US20050029666 Semiconductor device structural body and electronic device
02/10/2005US20050029665 Barrier-less integration with copper alloy
02/10/2005US20050029663 Polynorbornene foam insulation for integrated circuits
02/10/2005US20050029662 Depositing a capping (metal) layer on a copper interconnect in a semiconductor by electroless plating in two stages; prevents undeposition of the capping layer to provide a copper interconnect and device of high reliability; free of oxidation of the copper interconnect
02/10/2005US20050029661 Integrated circuit and associated test method
02/10/2005US20050029660 Adhesions of structures formed from materials of poor adhesion
02/10/2005US20050029659 Low resistance and reliable copper interconnects by variable doping
02/10/2005US20050029658 Circuit board and semiconductor device using the same
02/10/2005US20050029657 Enhanced die-up ball grid array and method for making the same
02/10/2005US20050029655 Semiconductor device
02/10/2005US20050029654 IC chip with nanowires
02/10/2005US20050029653 IC-chip having a protective structure
02/10/2005US20050029652 Interposer with integral heat sink
02/10/2005US20050029651 Semiconductor apparatus and method of manufacturing the same
02/10/2005US20050029650 Method for fabricating semiconductor components with thinned substrate, back side contacts and circuit side contacts
02/10/2005US20050029649 Integrated circuit package with overlapping bond fingers
02/10/2005US20050029648 Semiconductor device and an electronic device
02/10/2005US20050029646 Semiconductor device and method for dividing substrate
02/10/2005US20050029645 Stacked mass storage flash memory package
02/10/2005US20050029644 [multi-chip package and manufacturing method thereof]
02/10/2005US20050029642 Module with embedded semiconductor IC and method of fabricating the module
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