Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 23 - Details of semiconductor or other solid state devices
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
06/2005
06/09/2005US20050124185 Support for an integrated circuit package having a column grid array interconnect
06/09/2005US20050124181 Connector for making electrical contact at semiconductor scales
06/09/2005US20050124172 Process for making air gap containing semiconducting devices and resulting semiconducting device
06/09/2005US20050124164 Fine particle film forming apparatus and method and semiconductor device and manufacturing method for the same
06/09/2005US20050124158 Silver under-layers for electroless cobalt alloys
06/09/2005US20050124156 Semiconductor device and manufacturing process therefore
06/09/2005US20050124154 Method of forming copper interconnections for semiconductor integrated circuits on a substrate
06/09/2005US20050124152 Composite sacrificial material
06/09/2005US20050124150 Method for fabricating semiconductor device
06/09/2005US20050124148 Method for embedding a component in a base and forming a contact
06/09/2005US20050124147 Land grid array packaged device and method of forming same
06/09/2005US20050124142 Transposed split of ion cut materials
06/09/2005US20050124131 Method of forming an inductor with continuous metal deposition
06/09/2005US20050124112 Asymmetric-area memory cell
06/09/2005US20050124105 Semiconductor device and method of manufacturing the same
06/09/2005US20050124097 Integrated circuit with two phase fuse material and method of using and making same
06/09/2005US20050124095 Sram device having high aspect ratio cell boundary
06/09/2005US20050124094 Method of producing an electronic component
06/09/2005US20050124093 Fan out type wafer level package structure and method of the same
06/09/2005US20050124090 Manufacturing system and apparatus for balanced product flow with application to low-stress underfilling of flip-chip electronic devices
06/09/2005US20050124080 Monitoring low temperature rapid thermal anneal process using implanted wafers
06/09/2005US20050123845 Method of adjusting deviation of critical dimension of patterns
06/09/2005US20050123844 First and second alignment marks arranged one over the other; alignment based on periodicity of the Moire pattern
06/09/2005US20050123776 Thermosetting resin composition and photo-semiconductor encapsulant
06/09/2005US20050122698 Module board having embedded chips and components and method of forming the same
06/09/2005US20050122697 Enhancement of underfill physical properties by the addition of a thermotropic cellulose
06/09/2005US20050122691 Dissipating heat reliably in computer systems
06/09/2005US20050122690 Method and apparatus for attaching a processor and corresponding heat sink to a circuit board
06/09/2005US20050122688 Enhanced flow channel for component cooling in computer systems
06/09/2005US20050122687 Interlocking heat sink
06/09/2005US20050122686 Electronic card unit and method for removing heat from a heat-generating component on a printed circuit board
06/09/2005US20050122685 Cooling system and method employing multiple dedicated coolant conditioning units for cooling multiple electronics subsystems
06/09/2005US20050122683 Fan stand structure for central processing unit
06/09/2005US20050122557 Optical scanning device, image forming apparatus, and optical scanning method
06/09/2005US20050122516 Overlay metrology method and apparatus using more than one grating per measurement direction
06/09/2005US20050122288 Active matrix electroluminescent display devices, and their manufacture
06/09/2005US20050122204 Apparatus and method for electronic fuse with improved esd tolerance
06/09/2005US20050122198 Inductive device including bond wires
06/09/2005US20050122167 Power amplifier module for wireless communication devices
06/09/2005US20050122123 Zoom in pin nest structure, test vehicle having the structure, and method of fabricating the structure
06/09/2005US20050121809 Information storage apparatus and electronic device in which information storage apparatus is installed
06/09/2005US20050121808 Semiconductor device
06/09/2005US20050121807 Arrangement of a chip package constructed on a substrate and substrate for production of the same
06/09/2005US20050121805 Semiconductor device and a method of manufacturing the same
06/09/2005US20050121804 Chip structure with bumps and testing pads
06/09/2005US20050121803 Internally reinforced bond pads
06/09/2005US20050121802 Offset-bonded, multi-chip semiconductor device
06/09/2005US20050121801 Component
06/09/2005US20050121799 Semiconductor device manufacturing method and semiconductor device manufactured thereby
06/09/2005US20050121798 Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method
06/09/2005US20050121797 Configuration for testing the bonding positions of conductive drops and test method for using the same
06/09/2005US20050121796 Tape circuit substrate with reduced size of base film
06/09/2005US20050121795 Semiconductor component and corresponding fabrication/mounting method
06/09/2005US20050121794 Semiconductor constructions
06/09/2005US20050121793 Crossed power strapped layout for full CMOS circuit design
06/09/2005US20050121792 Interconnection structure and method for forming the same
06/09/2005US20050121791 Semiconductor device including multi-layered interconnection and method of manufacturing the device
06/09/2005US20050121790 Optimization of critical dimensions and pitch of patterned features in and above a substrate
06/09/2005US20050121789 Programmable structured arrays
06/09/2005US20050121788 Improved stress migration resistance; Multilayer; flat substrate, dielectric, connecting wires; miniaturization
06/09/2005US20050121787 Semiconductor device and method for manufacturing the same
06/09/2005US20050121786 Substrate, interlayer interconnection structure including porous insulation film in which a volume occupation ratio of pores of diameter greater than 0.6 nanometers is less than 30%, and conductive part containing metal; parasitic capacitance, degradation prevented
06/09/2005US20050121785 Material is applied onto lower edge of chip and regions of substrate abutting chip, then first continuous metal layer is applied on back side of chip and on material and edges, second sealing metal layer is applied by solvent-free process on those regions of first metal layer that cover material
06/09/2005US20050121784 Semiconductor device package utilizing proud interconnect material
06/09/2005US20050121783 Semiconductor device mounting structure
06/09/2005US20050121781 Semiconductor device and manufacturing method thereof
06/09/2005US20050121780 Structure of semiconductor element and its manufacturing process
06/09/2005US20050121779 Semiconductor device manufacturing method and manufacturing apparatus
06/09/2005US20050121778 Thinned die integrated circuit package
06/09/2005US20050121777 Semiconductor device
06/09/2005US20050121776 Integrated solder and heat spreader fabrication
06/09/2005US20050121775 Device and system for heat spreader with controlled thermal expansion
06/09/2005US20050121774 Electrical circuit apparatus and methods for assembling same
06/09/2005US20050121773 Method of manufacturing semiconductor device
06/09/2005US20050121772 Capacitor and method for manufacturing the same
06/09/2005US20050121771 Integrated chip package structure using metal substrate and method of manufacturing the same
06/09/2005US20050121770 Wafer-level electronic modules with integral connector contacts and methods of fabricating the same
06/09/2005US20050121769 Stacked integrated circuit packages and methods of making the packages
06/09/2005US20050121768 Silicon chip carrier with conductive through-vias and method for fabricating same
06/09/2005US20050121767 Integrated circuit package and method
06/09/2005US20050121766 Integrated circuit and method of manufacturing an integrated circuit and package
06/09/2005US20050121765 Multi-chips bumpless assembly package and manufacturing method thereof
06/09/2005US20050121764 Stackable integrated circuit packaging
06/09/2005US20050121761 Semiconductor device and method for fabricating the same
06/09/2005US20050121760 Semiconductor module
06/09/2005US20050121759 Semiconductor package with a chip on a support plate
06/09/2005US20050121758 Thin package for stacking integrated circuits
06/09/2005US20050121757 Integrated circuit package overlay
06/09/2005US20050121756 Dual gauge leadframe
06/09/2005US20050121755 Methods of fabricating integrated circuit conductive contact structures including grooves
06/09/2005US20050121754 Semiconductor package assembly and method for electrically isolating modules
06/09/2005US20050121753 Low-power semiconductor chip with separated power ring, method for manufacturing the same, and method for controlling the same
06/09/2005US20050121752 Chip package and electrical connection structure between chip and substrate
06/09/2005US20050121751 Carbon and halogen doped silicate glass dielectric layer and method for fabricating the same
06/09/2005US20050121750 Microelectronic device having disposable spacer
06/09/2005US20050121744 High density MIM capacitor structure and fabrication process
06/09/2005US20050121743 Memory cell comprising a semiconductor junction diode crystallized adjacent to a silicide
06/09/2005US20050121742 Semiconductor device including junction diode contacting contact-antifuse unit comprising silicide
06/09/2005US20050121741 Apparatus and method for electronic fuse with improved ESD tolerance
06/09/2005US20050121725 Electrostatic damage protection device
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