Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 23 - Details of semiconductor or other solid state devices
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
12/2005
12/15/2005WO2005119774A1 Method and apparatus for precise marking and placement of an object
12/15/2005WO2005119773A1 Module integration integrated circuits
12/15/2005WO2005119772A2 Coatings comprising carbon nanotubes
12/15/2005WO2005119771A1 Organic matrices containing nanomaterials to enhance bulk thermal conductivity
12/15/2005WO2005119770A1 Integrated circuit socket corner relief
12/15/2005WO2005119769A1 Method for construction of rigid photovoltaic modules
12/15/2005WO2005119768A1 Improved etch method
12/15/2005WO2005119767A1 Integrated circuit package with optimized mold shape
12/15/2005WO2005119766A2 Preparation of front contact for surface mounting
12/15/2005WO2005119765A2 Assembly including vertical and horizontal joined circuit panels
12/15/2005WO2005119757A2 Packaged integrated circuit devices
12/15/2005WO2005119754A1 Flexible leadframe structure and method for forming integrated circuit packages
12/15/2005WO2005119751A1 Semiconductor device and method for manufacturing same
12/15/2005WO2005119750A1 Semiconductor device and method for fabricating same
12/15/2005WO2005118464A1 Microelectromechanical systems (mems) devices integrated in a hermetically sealed package
12/15/2005WO2005117917A2 Thermal management system and computer arrangement
12/15/2005WO2005088712A3 Temperature control system which sprays liquid coolant droplets against an ic-module and directs radiation against the ic-module
12/15/2005WO2005081595A3 Preferential assymmetrical via positioning for printed circuit boards
12/15/2005WO2005079400A3 Buried guard ring and radiation hardened isolation structures and fabrication methods
12/15/2005WO2005067539A3 Multilayer ceramic substrate with single via anchored pad and method of forming
12/15/2005WO2005043176A3 Probe testing structure
12/15/2005WO2005027222A3 Assembly of an electrical component comprising an electrical insulation film on a substrate and method for producing said assembly
12/15/2005WO2004106221A3 Microelectromechanical device packages with integral heaters
12/15/2005US20050278679 Device for estimating number of board layers constituting board, system including the device, and method for estimating the same and program for executing the method
12/15/2005US20050278677 Novel test structure for automatic dynamic negative-bias temperature instability testing
12/15/2005US20050278674 Nested design approach
12/15/2005US20050277324 Memory metal springs for heatsink attachments
12/15/2005US20050277310 System and method for processor power delivery and thermal management
12/15/2005US20050277302 Advanced low dielectric constant barrier layers
12/15/2005US20050277298 Adhesion of copper and etch stop layer for copper alloy
12/15/2005US20050277293 Fabrication method of wafer level chip scale packages
12/15/2005US20050277288 Stackable semiconductor chip layer comprising prefabricated trench interconnect vias
12/15/2005US20050277287 Contact etching utilizing multi-layer hard mask
12/15/2005US20050277284 Method for manufacturing a semiconductor device
12/15/2005US20050277283 Chip structure and method for fabricating the same
12/15/2005US20050277281 Compliant interconnect and method of formation
12/15/2005US20050277280 Semiconductor device with a high thermal dissipation efficiency
12/15/2005US20050277279 Microfeature devices and methods for manufacturing microfeature devices
12/15/2005US20050277255 Compound semiconductor device and manufacturing method thereof
12/15/2005US20050277245 Method for forming bump on electrode pad with use of double-layered film
12/15/2005US20050277232 Diode junction poly fuse
12/15/2005US20050277231 Underfill and encapsulation of semicondcutor assemblies with materials having differing properties and methods of fabrication using stereolithography
12/15/2005US20050277230 Process for producing a chip arrangement provided with a molding compound
12/15/2005US20050277229 Chip packaging structure and method of making wafer level packaging
12/15/2005US20050277227 Chip scale package with open substrate
12/15/2005US20050277226 High density flip chip interconnections
12/15/2005US20050277220 Encapsulation for particle entrapment
12/15/2005US20050277210 Sequential unique marking
12/15/2005US20050276465 Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same
12/15/2005US20050276463 Visual inspection method and visual inspection apparatus
12/15/2005US20050276021 Memory module cooling
12/15/2005US20050276014 Thermal management arrangement with a low heat flux channel flow coupled to high heat flux channels
12/15/2005US20050275989 Cascaded gate-driven ESD clamp
12/15/2005US20050275980 RF generator with commutation inductor
12/15/2005US20050275741 Image pickup device and production method thereof
12/15/2005US20050275589 Thermal management system and method for thin membrane type antennas
12/15/2005US20050275456 RF generator with reduced size and weight
12/15/2005US20050275116 Reconstructed semiconductor wafers
12/15/2005US20050275115 Semiconductor device, circuit substrate, electro-optic device and electronic appliance
12/15/2005US20050275114 Semiconductor device and semiconductor apparatus
12/15/2005US20050275113 Embedded integrated circuit packaging structure
12/15/2005US20050275112 High power MCM package with improved planarity and heat dissipation
12/15/2005US20050275111 Contact etching utilizing partially recessed hard mask
12/15/2005US20050275110 Semiconductor device with a line and method of fabrication thereof
12/15/2005US20050275109 Semiconductor device and fabricating method thereof
12/15/2005US20050275108 Semiconductor device and method for fabricating the same
12/15/2005US20050275107 Contact etching utilizing multi-layer hard mask
12/15/2005US20050275105 Ultraviolet blocking layer
12/15/2005US20050275103 Integrated circuit comprising intermediate materials and corresponding components
12/15/2005US20050275102 Semiconductor device with low contact resistance and method for fabricating the same
12/15/2005US20050275101 Amorphus TiN
12/15/2005US20050275099 Semiconductor apparatus and method of manufacturing semiconductor apparatus
12/15/2005US20050275098 Lead-free conductive jointing bump
12/15/2005US20050275097 Method of forming a solder bump and the structure thereof
12/15/2005US20050275096 Pre-doped reflow interconnections for copper pads
12/15/2005US20050275095 Stress mitigation layer to reduce under bump stress concentration
12/15/2005US20050275094 Encapsulation of pin solder for maintaining accuracy in pin position
12/15/2005US20050275093 Semiconductor device and manufacturing method of the same
12/15/2005US20050275092 Semiconductor substrate and thin processing method for semiconductor substrate
12/15/2005US20050275091 Transfer molding of integrated circuit packages
12/15/2005US20050275090 Chip-component-mounted device and semiconductor device
12/15/2005US20050275089 Package and method for packaging an integrated circuit die
12/15/2005US20050275088 Circuit module and method for manufacturing the same
12/15/2005US20050275087 Internal package heat dissipator
12/15/2005US20050275086 Semiconductor package and process utilizing pre-formed mold cap and heatspreader assembly
12/15/2005US20050275085 Arrangement for reducing the electrical crosstalk on a chip
12/15/2005US20050275084 Compliant contact pin assembly and card system
12/15/2005US20050275083 Compliant contact pin assembly and card system
12/15/2005US20050275082 Vertical conduction power electronic device package and corresponding assembling method
12/15/2005US20050275081 Embedded chip semiconductor having dual electronic connection faces
12/15/2005US20050275080 Multi-chip module package structure
12/15/2005US20050275079 Wafer-level hermetic micro-device packages
12/15/2005US20050275078 High frequency multilayer integrated circuit
12/15/2005US20050275077 High density chip scale leadframe package and method of manufacturing the package
12/15/2005US20050275076 Semiconductor apparatus and method of manufacturing same, and method of detecting defects in semiconductor apparatus
12/15/2005US20050275075 Micro-electro-mechanical system (MEMS) package with spacer for sealing and method of manufacturing the same
12/15/2005US20050275074 Semiconductor package and method of manufacturing the same
12/15/2005US20050275073 Method and system for improved wire bonding
12/15/2005US20050275072 Package having bond-sealed underbump
12/15/2005US20050275071 Metal substrate apparatus, method of manufacturing an IC card module apparatus, and an IC card module apparatus
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