Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 23 - Details of semiconductor or other solid state devices
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
03/2014
03/27/2014WO2014045633A1 Imaging device, and endoscope equipped with imaging device
03/27/2014WO2014045518A1 Antenna, transmitting apparatus, receiving apparatus, three-dimensional integrated circuit, and non-contact communication system
03/27/2014WO2014045491A1 Wiring board and method for manufacturing same
03/27/2014WO2014045349A1 Semiconductor module
03/27/2014WO2014045139A1 Method of protecting an electrical component in a laminate
03/27/2014WO2014045090A1 Methods of forming iii-v semiconductor structures using multiple substrates, and semiconductor devices fabricated using such methods
03/27/2014WO2014044684A1 Moulding method for producing an electronic housing
03/27/2014WO2014044557A1 Optoelectronic component and method for producing an optoelectronic component
03/27/2014WO2014044463A1 Device having at least two wafers for detecting electromagnetic radiation and method for producing said device
03/27/2014WO2014044435A1 Manufacture of coated copper pillars
03/27/2014WO2014043929A1 Display device
03/27/2014WO2014016085A3 Cooling device and method for producing a cooling device and circuit assembly having a cooling device
03/27/2014WO2014004770A3 Integrated circuit device featuring an antifuse and method of making same
03/27/2014WO2013182591A3 Bonding agent comprising ferromagnetic heating particles, method for bonding two bodies using the bonding agent by means of induction heating of the heating particles, and corresponding electronic assembly
03/27/2014US20140089609 Interposer having embedded memory controller circuitry
03/27/2014US20140088281 Curable composition
03/27/2014US20140088251 Curable composition
03/27/2014US20140087553 Fabricating a Wafer Level Semiconductor Package Having a Pre-formed Dielectric Layer
03/27/2014US20140087548 Method of shielding through silicon vias in a passive interposer
03/27/2014US20140087522 Reducing Delamination Between an Underfill and a Buffer Layer in a Bond Structure
03/27/2014US20140087521 Wafer level chip scale packaging
03/27/2014US20140087519 Package process and package structure
03/27/2014US20140085758 Integrated circuit device and method of enabling thermal regulation within an integrated circuit device
03/27/2014US20140085599 Assembling thin silicon chips on a contact lens
03/27/2014US20140084491 Method for manufacturing electronic device and electronic device
03/27/2014US20140084490 Dicing tape-integrated wafer back surface protective film
03/27/2014US20140084489 Assembling thin silicon chips on a contact lens
03/27/2014US20140084487 PoP STRUCTURE WITH ELECTRICALLY INSULATING MATERIAL BETWEEN PACKAGES
03/27/2014US20140084486 Reliable interconnect for semiconductor device
03/27/2014US20140084485 Reliable packaging and interconnect structures
03/27/2014US20140084484 Semiconductor package and fabrication method thereof
03/27/2014US20140084483 Package structure and manufacturing method thereof
03/27/2014US20140084482 Micro device stabilization post
03/27/2014US20140084481 System and method of novel encapsulated multi metal branch foot structures for advanced back end of line
03/27/2014US20140084480 Semiconductor package substrates having layered circuit segments and related methods
03/27/2014US20140084479 Integrated Circuit Formed Using Spacer-Like Copper Deposition
03/27/2014US20140084478 Mold chase for integrated circuit package assembly and associated techniques and configurations
03/27/2014US20140084477 Noise attenuation wall
03/27/2014US20140084476 Thermal Dissipation Through Seal Rings in 3DIC Structure
03/27/2014US20140084475 Semiconductor package substrates having pillars and related methods
03/27/2014US20140084474 Method for forming a vertical electrical connection in a layered semiconductor structure
03/27/2014US20140084473 Semiconductor devices and methods of fabricating the same
03/27/2014US20140084472 Compound dielectric anti-copper-diffusion barrier layer for copper connection and manufacturing method thereof
03/27/2014US20140084471 Interconnect Structures Comprising Flexible Buffer Layers
03/27/2014US20140084470 Seed Layer Structure and Method
03/27/2014US20140084469 Method of semiconductor integrated circuit fabrication
03/27/2014US20140084468 Semiconductor device connected by anisotropic conductive film
03/27/2014US20140084467 Forming functionalized carrier structures with coreless packages
03/27/2014US20140084465 System and method of novel mx to mx-2
03/27/2014US20140084464 Passivation Scheme
03/27/2014US20140084463 Method of fabricating semiconductor package structure
03/27/2014US20140084462 Wafer Level Semiconductor Package
03/27/2014US20140084461 Flux materials for heated solder placement and associated techniques and configurations
03/27/2014US20140084460 Contact bumps methods of making contact bumps
03/27/2014US20140084459 Multiple Die Packaging Interposer Structure and Method
03/27/2014US20140084458 Chip package and method for forming the same
03/27/2014US20140084457 Bump structures, electrical connection structures, and methods of forming the same
03/27/2014US20140084456 Semiconductor packages, methods of manufacturing semiconductor packages, and systems including semiconductor packages
03/27/2014US20140084455 Semiconductor package and fabrication method thereof
03/27/2014US20140084454 Direct multiple substrate die assembly
03/27/2014US20140084453 Overcoming chip warping to enhance wetting of solder bumps and flip chip attaches in a flip chip package
03/27/2014US20140084452 Element mounting board and semiconductor module
03/27/2014US20140084451 Split Loop Cut Pattern For Spacer Process
03/27/2014US20140084450 Processes for multi-layer devices utilizing layer transfer
03/27/2014US20140084449 Semiconductor Housing with Rear-Side Structuring
03/27/2014US20140084448 Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly
03/27/2014US20140084447 Power module package
03/27/2014US20140084446 Semiconductor package and semiconductor devices with the same
03/27/2014US20140084445 Thermal Dissipation Through Seal Rings in 3DIC Structure
03/27/2014US20140084444 Thermal Dissipation Through Seal Rings in 3DIC Structure
03/27/2014US20140084443 Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly
03/27/2014US20140084442 Semiconductor Packages Having a Guide Wall and Related Systems and Methods
03/27/2014US20140084441 Stacked-die package including die in package substrate
03/27/2014US20140084440 Semiconductor device
03/27/2014US20140084439 Semiconductor device, electronic device and method for fabricating the semiconductor device
03/27/2014US20140084438 Semiconductor device and method of manufacturing same
03/27/2014US20140084437 Semiconductor device including semiconductor chip mounted on lead frame
03/27/2014US20140084436 Semiconductor device and method of manufacturing the same
03/27/2014US20140084435 Resin-encapsulated semiconductor device and method of manufacturing the same
03/27/2014US20140084434 Semiconductor device
03/27/2014US20140084433 Semiconductor Device Having a Clip Contact
03/27/2014US20140084432 Method and apparatus for multi-chip structure semiconductor package
03/27/2014US20140084431 Semiconductor Package with Heat Spreader
03/27/2014US20140084430 Semiconductor chip and film and tab package comprising the chip and film
03/27/2014US20140084429 Extremely thin package
03/27/2014US20140084428 Integrated circuit with electrical through-contact and method for producing electrical through-contact
03/27/2014US20140084426 Substrate member and method of manufacturing chip
03/27/2014US20140084425 Perimeter trench sensor array package
03/27/2014US20140084424 Semiconductor Device with Protective Structure Around Semiconductor Die for Localized Planarization of Insulating Layer
03/27/2014US20140084416 Stacked Package and Method of Manufacturing the Same
03/27/2014US20140084413 Package substrate and method of fabricating the same
03/27/2014US20140084375 Semiconductor Devices Having Back Side Bonding Structures
03/27/2014US20140084373 ESD Clamp in Integrated Circuits
03/27/2014US20140084302 Integrated circuit, a chip package and a method for manufacturing an integrated circuit
03/27/2014US20140082936 Method of manufacturing a wiring substrate
03/27/2014DE112012002736T5 In situ gebaute kontaktstift-rasterfelder für kernlose substrate und verfahren zu deren herstellung Built in situ-pin-grids for coreless substrates and process for their production
03/27/2014DE112009004375B4 Halbleitervorrichtung Semiconductor device
03/27/2014DE112006000992B4 Siliziumnitridsubstrat, Herstellungsverfahren des Siliziumnitridsubstrats, Siliziumnitridleiterplatte unter Verwendung des Siliziumnitridsubstrats und Halbleitermodul, das diese verwendet Silicon nitride substrate, method of manufacturing the Siliziumnitridsubstrats, Siliziumnitridleiterplatte using the Siliziumnitridsubstrats and semiconductor module that uses this
03/27/2014DE10334384B4 Chipvorrichtung Chip device
03/27/2014DE102013210850B3 Method for manufacturing semiconductor module, involves carrying out removal of adhesive upper surface of circuit carrier, locating projections from bottom face of carrier, and inserting circuit carrier in through-holes of adhesion carrier
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