Patents
Patents for H01L 23 - Details of semiconductor or other solid state devices (226,155)
04/2014
04/29/2014US8710664 Wafer-level chip scale package
04/29/2014US8710663 Method of manufacturing semiconductor device and semiconductor device
04/29/2014US8710662 Light-reflective anisotropic conductive paste and light-emitting device
04/29/2014US8710661 Methods for selective reverse mask planarization and interconnect structures formed thereby
04/29/2014US8710660 Hybrid interconnect scheme including aluminum metal line in low-k dielectric
04/29/2014US8710659 Semiconductor device and method of manufacturing the same
04/29/2014US8710658 Under bump passive components in wafer level packaging
04/29/2014US8710656 Redistribution layer (RDL) with variable offset bumps
04/29/2014US8710655 Die packages and systems having the die packages
04/29/2014US8710654 Semiconductor device and manufacturing method thereof
04/29/2014US8710653 Chip on chip semiconductor device including an underfill layer having a resin containing an amine-based curing agent
04/29/2014US8710652 Embedded package and method for manufacturing the same
04/29/2014US8710650 Semiconductor devices having through electrodes and methods of fabricating the same
04/29/2014US8710649 Wafer level package and fabrication method
04/29/2014US8710648 Wafer level packaging structure with large contact area and preparation method thereof
04/29/2014US8710647 Semiconductor device having a first conductive member connecting a chip to a wiring board pad and a second conductive member connecting the wiring board pad to a land on an insulator covering the chip and the wiring board
04/29/2014US8710646 Power module
04/29/2014US8710645 Area reduction for surface mount package chips
04/29/2014US8710644 Semiconductor unit having a power semiconductor and semiconductor apparatus using the same
04/29/2014US8710643 Electronic package with fluid flow barriers
04/29/2014US8710642 Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus
04/29/2014US8710641 Combination for composite layered chip package
04/29/2014US8710640 Integrated circuit packaging system with heat slug and method of manufacture thereof
04/29/2014US8710639 Semiconductor element-embedded wiring substrate
04/29/2014US8710638 Socket type MEMS device with stand-off portion
04/29/2014US8710637 Semiconductor device and method of manufacturing the same
04/29/2014US8710636 Lead frame array package with flip chip die attach
04/29/2014US8710635 Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die
04/29/2014US8710634 Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof
04/29/2014US8710629 Apparatus and method for controlling semiconductor die warpage
04/29/2014US8710595 Semiconductor device
04/29/2014US8710594 Integrated circuit devices having conductive structures with different cross sections
04/29/2014US8710591 Semiconductor chip, stack module, and memory card
04/29/2014US8710590 Electronic component and a system and method for producing an electronic component
04/29/2014US8710589 Semiconductor device
04/29/2014US8710567 Semiconductor device and manufacturing method thereof
04/29/2014US8710554 Biosensor kit
04/29/2014US8710553 Method and apparatus for connecting signal lines of multiple layers to certain contacts while preventing connections with other contacts
04/29/2014US8710540 LED package with top and bottom electrodes
04/29/2014US8709945 Area efficient through-hole connections
04/29/2014US8709935 Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties
04/29/2014US8709932 Integrated circuit packaging system with interconnects and method of manufacture thereof
04/29/2014US8709841 Woven mesh substrate with semiconductor elements, and method and device for manufacturing the same
04/29/2014US8708222 Method for producing a finishing layer containing a window for a portable data storage medium and said finishing layer
04/29/2014CA2507651C Method, system and apparatus for cooling high power density devices
04/24/2014WO2014062974A1 Heat sink attachment apparatus and method
04/24/2014WO2014062843A1 Silicone polymers with high refractive indices and extended pot life
04/24/2014WO2014062602A1 Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs
04/24/2014WO2014062135A1 Encapsulation barrier stack
04/24/2014WO2014061725A1 Method for manufacturing composite hollow container, and composite hollow container
04/24/2014WO2014061643A1 Method for manufacturing semiconductor device, and semiconductor device
04/24/2014WO2014061588A1 Substrate for power module with heat sink, power module with heat sink, and method for producing substrate for power module with heat sink
04/24/2014WO2014061531A1 Substrate device and method for manufacturing same
04/24/2014WO2014061517A1 Curable composition containing silica particles, cured product thereof, and semiconductor sealing material using same
04/24/2014WO2014061426A1 Semiconductor device
04/24/2014WO2014061373A1 Semiconductor device and fabrication method therefor
04/24/2014WO2014061178A1 Cooling structure and heat generating body
04/24/2014WO2014059974A2 Multifunction microelectronic component and method for producing such component
04/24/2014WO2014059700A1 Cof baseband, manufacturing method thereof, and liquid crystal display module
04/24/2014WO2014022619A3 Dual solder layer for fluidic self assembly and electrical component substrate and method employing same
04/24/2014WO2012122388A3 Chip-last embedded interconnect structures and methods of making the same
04/24/2014US20140114043 Curable composition
04/24/2014US20140114042 Curable composition
04/24/2014US20140113447 Electrical Connection for Chip Scale Packaging
04/24/2014US20140113414 Semiconductor mounting device and method for manufacturing semiconductor mounting device
04/24/2014US20140113413 Semiconductor wafer mounting method and semiconductor wafer mounting apparatus
04/24/2014US20140113411 Semiconductor device and method for manufacturing thereof
04/24/2014US20140111976 Silicone resin
04/24/2014US20140111956 Joining method using metal foam, method of manufacturing semiconductor device, and semiconductor device
04/24/2014US20140111274 Programmable revision cell id system and method
04/24/2014US20140111245 Integrated circuit design protecting device and method thereof
04/24/2014US20140111234 Die, Chip, Method for Driving a Die or a Chip and Method for Manufacturing a Die or a Chip
04/24/2014US20140110867 Substrate and Method for Cutting the Substrate
04/24/2014US20140110866 System and method of chip package build-up
04/24/2014US20140110865 Optoelectronic device and method for the production thereof
04/24/2014US20140110864 Chip arrangement and a method for forming a chip arrangement
04/24/2014US20140110862 TSV Formation
04/24/2014US20140110861 Semiconductor Device Having an Interconnect Structure with TSV Using Encapsulant for Structural Support
04/24/2014US20140110860 Semiconductor Package and Method of Mounting Semiconductor Die to Opposite Sides of TSV Substrate
04/24/2014US20140110859 Embedding thin chips in polymer
04/24/2014US20140110858 Embedded chip packages and methods for manufacturing an embedded chip package
04/24/2014US20140110856 Fan-Out Wafer Level Package Structure
04/24/2014US20140110855 Cd control
04/24/2014US20140110854 Semiconductor dies with reduced area consumption
04/24/2014US20140110853 Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium
04/24/2014US20140110852 Active matrix substrate, and display device
04/24/2014US20140110851 Semiconductor Device
04/24/2014US20140110850 Semiconductor device and method for manufacturing the same
04/24/2014US20140110849 Copper-Titanium Alloy Sputtering Target, Semiconductor Wiring Line Formed Using the Sputtering Target, and Semiconductor Element and Device Each Equipped with the Semiconductor Wiring Line
04/24/2014US20140110848 Strong, heat stable junction
04/24/2014US20140110847 Bump-on-trace interconnection structure for flip-chip packages
04/24/2014US20140110846 Dual hard mask lithography process
04/24/2014US20140110845 Damascene gap structure
04/24/2014US20140110844 Wire bondable surface for microelectronic devices
04/24/2014US20140110843 Semiconductor Unit with Submount for Semiconductor Device
04/24/2014US20140110842 Using a double-cut for mechanical protection of a wafer-level chip scale package (wlcsp)
04/24/2014US20140110841 Semiconductor Packages with Integrated Antenna and Methods of Forming Thereof
04/24/2014US20140110840 Semiconductor Packages with Integrated Antenna and Method of Forming Thereof
04/24/2014US20140110839 Metal Bump Joint Structure
04/24/2014US20140110838 Semiconductor devices and processing methods