| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 03/14/2000 | US6037647 Semiconductor device having an epitaxial substrate and a fabrication process thereof |
| 03/14/2000 | US6037646 High-frequency GaAs substrate based schottky barrier diodes |
| 03/14/2000 | US6037640 Ultra-shallow semiconductor junction formation |
| 03/14/2000 | US6037639 Fabrication of integrated devices using nitrogen implantation |
| 03/14/2000 | US6037638 Semiconductor memory device |
| 03/14/2000 | US6037637 BiCMOS logical integrated circuit |
| 03/14/2000 | US6037635 Semiconductor device with transistors formed on different layers |
| 03/14/2000 | US6037634 Semiconductor device with first and second elements formed on first and second portions |
| 03/14/2000 | US6037633 Semiconductor device |
| 03/14/2000 | US6037632 Semiconductor device |
| 03/14/2000 | US6037630 Semiconductor device with gate electrode portion and method of manufacturing the same |
| 03/14/2000 | US6037629 Trench transistor and isolation trench |
| 03/14/2000 | US6037628 Semiconductor structures with trench contacts |
| 03/14/2000 | US6037627 MOS semiconductor device |
| 03/14/2000 | US6037626 Semiconductor neuron with variable input weights |
| 03/14/2000 | US6037625 Semiconductor device with salicide structure and fabrication method thereof |
| 03/14/2000 | US6037624 Process and structure of a modified T-shaped capacitor having a rough top surface |
| 03/14/2000 | US6037623 Polycrystalline silicon resistors for integrated circuits |
| 03/14/2000 | US6037620 DRAM cell with transfer device extending along perimeter of trench storage capacitor |
| 03/14/2000 | US6037619 Field effect transistor and high-frequency power amplifier having same |
| 03/14/2000 | US6037617 SOI IGFETs having raised integration level |
| 03/14/2000 | US6037616 Bipolar transistor having base contact layer in contact with lower surface of base layer |
| 03/14/2000 | US6037615 Metal semiconductor FET having doped A1GaAs layer between channel layer and A1GaAs buffer layer |
| 03/14/2000 | US6037611 Thin film transistor and its fabrication |
| 03/14/2000 | US6037610 Transistor and semiconductor device having columnar crystals |
| 03/14/2000 | US6037605 Semiconductor device and method of manufacturing the same |
| 03/14/2000 | US6037602 Photovoltaic generator circuit and method of making same |
| 03/14/2000 | US6037601 Electron beam illumination device, and exposure apparatus with electron beam illumination device |
| 03/14/2000 | US6037599 Ion implantation apparatus and fabrication method for semiconductor device |
| 03/14/2000 | US6037588 Method for testing semiconductor device |
| 03/14/2000 | US6037278 Method of manufacturing semiconductor devices having multi-level wiring structure |
| 03/14/2000 | US6037277 Limited-volume apparatus and method for forming thin film aerogels on semiconductor substrates |
| 03/14/2000 | US6037276 Improving lithography patterning process by forming an oxynitride layer antireflective coatings, forming a nitride layer and a photoresist layer, exposing to electromagnetic radiation |
| 03/14/2000 | US6037275 Nanoporous silica via combined stream deposition |
| 03/14/2000 | US6037274 Method for forming insulating film |
| 03/14/2000 | US6037273 Method and apparatus for insitu vapor generation |
| 03/14/2000 | US6037272 Apparatus and method for low pressure chemical vapor deposition using multiple chambers and vacuum pumps |
| 03/14/2000 | US6037271 Low haze wafer treatment process |
| 03/14/2000 | US6037270 Purifying a wafer by dipping in an acid aqueous solution and irradiating ultraviolet rays upon it to remove an oxide film formed on a surface of the semiconductor substrate |
| 03/14/2000 | US6037269 Etching methods of silicon nitride films employed in microelectronic devices |
| 03/14/2000 | US6037268 Method for etching tantalum oxide |
| 03/14/2000 | US6037267 Method of etching metallic film for semiconductor devices |
| 03/14/2000 | US6037266 Four steps etching insitu with a high density plasma, and applying a first transformer coupled plasma power and a bias power |
| 03/14/2000 | US6037265 Etching the conductive layer in a high density plasma comprising a halogen gas and carbon monoxide to produce a supports |
| 03/14/2000 | US6037264 Method for removing redeposited veils from etched platinum |
| 03/14/2000 | US6037263 Plasma enhanced CVD deposition of tungsten and tungsten compounds |
| 03/14/2000 | US6037262 Process for forming vias, and trenches for metal lines, in multiple dielectric layers of integrated circuit structure |
| 03/14/2000 | US6037261 Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material |
| 03/14/2000 | US6037260 An aqueous acidic solution comprising boehmite, a hydroxide of aluminum, pseudoboehmite, alumina |
| 03/14/2000 | US6037259 Method for forming identifying characters on a silicon wafer |
| 03/14/2000 | US6037258 Three step deposition sequence featuring an in situ, cool down cycle, performed after deposition of a lower portion of a plasma deposited, copper seed layer, and prior to the insitu, plsama deposition of upper portion of copper seed layer |
| 03/14/2000 | US6037257 Sputter deposition and annealing of copper alloy metallization |
| 03/14/2000 | US6037256 Method for producing a noble metal-containing structure on a substrate, and semiconductor component having such a noble metal-containing structure |
| 03/14/2000 | US6037255 Method for making integrated circuit having polymer interlayer dielectric |
| 03/14/2000 | US6037254 Method of making a surface protective layer for improved silicide formation |
| 03/14/2000 | US6037253 Forming interconnects that are smaller than the photolithographic and etching dimensional limits; the sidewall spacer allows interconnects to be formed closer together than possible using conventional photolithography |
| 03/14/2000 | US6037252 Method of titanium nitride contact plug formation |
| 03/14/2000 | US6037251 Forming a silicon-rich oxide layer on a substrate, covering it with a metal layer and an antireflective titanium coating, partially etching the both layers, forming an ozone tetraethoxysilane layer to form bumps and spin-on glass layer |
| 03/14/2000 | US6037250 Depositing a copper layer, covering it with first dielectric interlayer, forming a photoresist film serving as a mask, and etching the copper layer using the mask to form hole for exposing a portion of first level copper interconnects |
| 03/14/2000 | US6037249 Method for forming air gaps for advanced interconnect systems |
| 03/14/2000 | US6037248 Method of fabricating integrated circuit wiring with low RC time delay |
| 03/14/2000 | US6037247 Method of manufacturing semiconductor device having a self aligned contact |
| 03/14/2000 | US6037246 Method of making a contact structure |
| 03/14/2000 | US6037245 High-speed semiconductor device having a dual-layer gate structure and a fabrication process thereof |
| 03/14/2000 | US6037244 Method of manufacturing a semiconductor device using advanced contact formation |
| 03/14/2000 | US6037243 Method for manufacturing silicon nanometer structure using silicon nitride film |
| 03/14/2000 | US6037242 Forming a buffer layer of aluminum-indium-arsenic on a gallium-arsenic substrate in an amorphous state, annealing the amorphous buffer layer to crystallize into single crystal, forming second and third single crystal buffer layers |
| 03/14/2000 | US6037241 Apparatus and method for depositing a semiconductor material |
| 03/14/2000 | US6037239 Method for making a contact structure for a polysilicon filled trench isolation |
| 03/14/2000 | US6037238 Process to reduce defect formation occurring during shallow trench isolation formation |
| 03/14/2000 | US6037237 Trench isolation methods utilizing composite oxide films |
| 03/14/2000 | US6037236 Regeneration of alignment marks after shallow trench isolation with chemical mechanical polishing |
| 03/14/2000 | US6037235 Forming a silicon nitride film on a silicon surface of a substrate, while heating the substrate, exposing silicon nitride film to hydrogen and nitrogen, forming a capacitor electrode above the exposed nitride film |
| 03/14/2000 | US6037234 Method of fabricating capacitor |
| 03/14/2000 | US6037233 Metal-encapsulated polysilicon gate and interconnect |
| 03/14/2000 | US6037232 Semiconductor device having elevated silicidation layer and process for fabrication thereof |
| 03/14/2000 | US6037231 Method for forming a MOS structure having sidewall source/drain and embedded gate |
| 03/14/2000 | US6037230 Method to reduce diode capacitance of short-channel MOSFETS |
| 03/14/2000 | US6037229 High-voltage device substrate structure and method of fabrication |
| 03/14/2000 | US6037228 Method of fabricating self-aligned contact window which includes forming a undoped polysilicon spacer that extends into a recess of the gate structure |
| 03/14/2000 | US6037227 Method of making high density mask ROM having a two level bit line |
| 03/14/2000 | US6037226 Method of making contactless nonvolatile semiconductor memory with asymmetrical floating gate |
| 03/14/2000 | US6037225 Manufacturing method for mask ROM devices |
| 03/14/2000 | US6037224 Method for growing dual oxide thickness using nitrided oxides for oxidation suppression |
| 03/14/2000 | US6037223 Stack gate flash memory cell featuring symmetric self aligned contact structures |
| 03/14/2000 | US6037222 Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology |
| 03/14/2000 | US6037221 Device and fabricating method of non-volatile memory |
| 03/14/2000 | US6037220 Method of increasing the surface area of a DRAM capacitor structure via the use of hemispherical grained polysilicon |
| 03/14/2000 | US6037219 One step in situ doped amorphous silicon layers used for selective hemispherical grain silicon formation for crown shaped capacitor applications |
| 03/14/2000 | US6037218 Semiconductor processing methods of forming stacked capacitors |
| 03/14/2000 | US6037217 Method of fabricating a capacitor electrode structure in a dynamic random-access memory device |
| 03/14/2000 | US6037216 Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process |
| 03/14/2000 | US6037215 Fabricating methods including capacitors on capping layer |
| 03/14/2000 | US6037214 Method of fabricating a capacitor |
| 03/14/2000 | US6037213 Method for making cylinder-shaped capacitors for dynamic random access memory |
| 03/14/2000 | US6037212 Method of fabricating a semiconductor memory cell having a tree-type capacitor |
| 03/14/2000 | US6037211 Method of fabricating contact holes in high density integrated circuits using polysilicon landing plug and self-aligned etching processes |
| 03/14/2000 | US6037210 Memory cell with transfer device node in selective polysilicon |
| 03/14/2000 | US6037209 Method for producing a DRAM cellular arrangement |
| 03/14/2000 | US6037208 Method for forming a deep trench capacitor of a DRAM cell |