| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 03/21/2000 | US6040909 Surface position detecting system and device manufacturing method using the same |
| 03/21/2000 | US6040894 Projection exposure apparatus and device manufacturing method |
| 03/21/2000 | US6040893 Scanning exposure method and apparatus for controlling acceleration and deceleration of a masking device |
| 03/21/2000 | US6040892 Multiple image reticle for forming layers |
| 03/21/2000 | US6040810 Display device having display and imaging pixels sandwiched between same substrates |
| 03/21/2000 | US6040735 Reference voltage generators including first and second transistors of same conductivity type |
| 03/21/2000 | US6040712 Apparatus and method for protecting a circuit during a hot socket condition |
| 03/21/2000 | US6040704 Probe unit and inspection head |
| 03/21/2000 | US6040675 Supporting apparatus using magnetic power |
| 03/21/2000 | US6040633 Oxide wire bond insulation in semiconductor assemblies |
| 03/21/2000 | US6040631 Method of improved cavity BGA circuit package |
| 03/21/2000 | US6040630 Integrated circuit package for flip chip with alignment preform feature and method of forming same |
| 03/21/2000 | US6040629 Semiconductor integrated circuit having silicided elements of short length |
| 03/21/2000 | US6040627 Semiconductor device and method of manufacturing semiconductor device |
| 03/21/2000 | US6040626 Semiconductor package |
| 03/21/2000 | US6040622 Semiconductor package using terminals formed on a conductive layer of a circuit board |
| 03/21/2000 | US6040619 Semiconductor device including antireflective etch stop layer |
| 03/21/2000 | US6040618 Multi-chip module employing a carrier substrate with micromachined alignment structures and method of forming |
| 03/21/2000 | US6040617 Structure to provide junction breakdown stability for deep trench devices |
| 03/21/2000 | US6040616 Device and method of forming a metal to metal capacitor within an integrated circuit |
| 03/21/2000 | US6040615 Semiconductor device with moisture resistant fuse portion |
| 03/21/2000 | US6040614 Semiconductor integrated circuit including a capacitor and a fuse element |
| 03/21/2000 | US6040613 Antireflective coating and wiring line stack |
| 03/21/2000 | US6040610 Semiconductor device |
| 03/21/2000 | US6040609 Process for integrating, in a single semiconductor chip, MOS technology devices with different threshold voltages |
| 03/21/2000 | US6040607 Self aligned method for differential oxidation rate at shallow trench isolation edge |
| 03/21/2000 | US6040606 Integrated circuit structure with dual thickness cobalt silicide layers and method for its manufacture |
| 03/21/2000 | US6040605 Semiconductor memory device |
| 03/21/2000 | US6040604 Semiconductor component comprising an electrostatic-discharge protection device |
| 03/21/2000 | US6040602 Formation of lightly doped regions under a gate |
| 03/21/2000 | US6040601 High voltage device |
| 03/21/2000 | US6040600 Trenched high breakdown voltage semiconductor device |
| 03/21/2000 | US6040599 Insulated trench semiconductor device with particular layer structure |
| 03/21/2000 | US6040598 High-breakdown-voltage semiconductor apparatus |
| 03/21/2000 | US6040597 Isolation boundaries in flash memory cores |
| 03/21/2000 | US6040596 Dynamic random access memory devices having improved peripheral circuit resistors therein |
| 03/21/2000 | US6040595 Structure of a non-destructive readout dynamic random access memory |
| 03/21/2000 | US6040594 High permittivity ST thin film and a capacitor for a semiconductor integrated circuit having such a thin film |
| 03/21/2000 | US6040589 Semiconductor device having larger contact hole area than an area covered by contact electrode in the hole |
| 03/21/2000 | US6040585 Method for detecting wafer orientation during transport |
| 03/21/2000 | US6040583 Electron beam exposure method using a moving stage |
| 03/21/2000 | US6040582 Ion beam focuser for an ion implanter analyzer |
| 03/21/2000 | US6040518 Wafer temperature monitoring device utilizing flexible thermocouple |
| 03/21/2000 | US6040418 Fluorinated polyimides, laminated substrates and polyamic acid solutions |
| 03/21/2000 | US6040249 Method of improving diffusion barrier properties of gate oxides by applying ions or free radicals of nitrogen in low energy |
| 03/21/2000 | US6040248 Anisotropically etching contact/via openings in the layer with an etchant containing o2 and cl2. cl2 permits the achievement of essentially vertical sidewalls on the openings etched in the organic polymeric dielectric |
| 03/21/2000 | US6040247 Controlling a flow rate of carrier gas at an etcher having a mixture of gases, the mixture including cf4, a polymer forming gas and a carrier gas |
| 03/21/2000 | US6040245 IC mechanical planarization process incorporating two slurry compositions for faster material removal times |
| 03/21/2000 | US6040243 Into dielectric layers in the fabrication of dual damascene interconnects in the manufacture of an integrated circuit device. |
| 03/21/2000 | US6040242 Method of manufacturing a contact plug |
| 03/21/2000 | US6040241 Method of avoiding sidewall residue in forming connections |
| 03/21/2000 | US6040240 Substrate having the copper interconnect is exposed to atmosphere after the substrate is cooled to a temperature below 160.degree. c. under a non-oxidizable atmosphere. |
| 03/21/2000 | US6040239 Non-oxidizing touch contact interconnect for semiconductor test systems and method of fabrication |
| 03/21/2000 | US6040238 Thermal annealing for preventing polycide void |
| 03/21/2000 | US6040237 Fabrication of a SiC semiconductor device comprising a pn junction with a voltage absorbing edge |
| 03/21/2000 | US6040236 Method for manufacturing silicon thin film conductive element |
| 03/21/2000 | US6040235 Methods and apparatus for producing integrated circuit devices |
| 03/21/2000 | US6040234 Method of manufacturing semiconductor device without bird beak effect |
| 03/21/2000 | US6040233 Method of making a shallow trench isolation with thin nitride as gate dielectric |
| 03/21/2000 | US6040232 Method of manufacturing shallow trench isolation |
| 03/21/2000 | US6040231 Method of fabricating a shallow trench isolation structure which includes using a salicide process to form an aslope periphery at the top corner of the substrate |
| 03/21/2000 | US6040230 Method of forming a nano-rugged silicon-containing layer |
| 03/21/2000 | US6040229 Method for manufacturing a solid electrolytic capacitor array |
| 03/21/2000 | US6040228 Capacitance-forming method |
| 03/21/2000 | US6040227 IPO deposited with low pressure O3 -TEOS for planarization in multi-poly memory technology |
| 03/21/2000 | US6040226 Method for fabricating a thin film inductor |
| 03/21/2000 | US6040225 Method of fabricating polysilicon based resistors in Si-Ge heterojunction devices |
| 03/21/2000 | US6040224 Method of manufacturing semiconductor devices |
| 03/21/2000 | US6040223 Method for making improved polysilicon FET gate electrodes having composite sidewall spacers using a trapezoidal-shaped insulating layer for more reliable integrated circuits |
| 03/21/2000 | US6040222 Method for fabricating an electrostatistic discharge protection device to protect an integrated circuit |
| 03/21/2000 | US6040221 Semiconductor processing methods of forming a buried contact, a conductive line, an electrical connection to a buried contact area, and a field effect transistor gate |
| 03/21/2000 | US6040220 Asymmetrical transistor formed from a gate conductor of unequal thickness |
| 03/21/2000 | US6040219 Method of fabricating power semiconductor device using semi-insulating polycrystalline silicon (SIPOS) film |
| 03/21/2000 | US6040218 Two square NVRAM cell |
| 03/21/2000 | US6040217 Fabricating method of an ultra-fast pseudo-dynamic nonvolatile flash memory |
| 03/21/2000 | US6040216 Method (and device) for producing tunnel silicon oxynitride layer |
| 03/21/2000 | US6040215 Method of manufacturing semiconductor device including memory cell having transistor |
| 03/21/2000 | US6040214 Method for making field effect transistors having sub-lithographic gates with vertical side walls |
| 03/21/2000 | US6040213 Polysilicon mini spacer for trench buried strap formation |
| 03/21/2000 | US6040212 Methods of forming trench-gate semiconductor devices using sidewall implantation techniques to control threshold voltage |
| 03/21/2000 | US6040211 Semiconductors having defect denuded zones |
| 03/21/2000 | US6040210 2F-square memory cell for gigabit memory applications |
| 03/21/2000 | US6040209 Semiconductor memory device and method of forming transistors in a peripheral circuit of the semiconductor memory device |
| 03/21/2000 | US6040208 Angled ion implantation for selective doping |
| 03/21/2000 | US6040207 Oxide formation technique using thin film silicon deposition |
| 03/21/2000 | US6040206 The conductive layer has a layered structure of an al-containing metal film and an n-containing mo film. |
| 03/21/2000 | US6040205 Apparatus and method for controlling the depth of immersion of a semiconductor element in an exposed surface of a viscous fluid |
| 03/21/2000 | US6040204 Method of stacking chips with a removable connecting layer |
| 03/21/2000 | US6040203 Clock skew minimization and method for integrated circuits |
| 03/21/2000 | US6040202 Color linear charge coupled device and method for driving the same |
| 03/21/2000 | US6040201 Titanium nitride, titanium oxide |
| 03/21/2000 | US6040200 Method of fabricating semiconductor device having stacked-layered substrate |
| 03/21/2000 | US6040199 Semiconductor test structure for estimating defects at isolation edge and test method using the same |
| 03/21/2000 | US6040120 Thermal processing apparatus |
| 03/21/2000 | US6040119 Exposing through a mask a dried photoresist coated onto substrate to actinic radiation, then baking for a time at a low temperature prior to final development of photoresist to provide accurate image |
| 03/21/2000 | US6040114 Exposing photosensitive film coated on substrate with a radiation beam to form a pattern of successive butting unit regions and resulting butting portions therebetween overlying isolation regions of integrated circuit, developing, etching |
| 03/21/2000 | US6040112 Photoresist composition |
| 03/21/2000 | US6040110 Process and apparatus for the removal of resist |
| 03/21/2000 | US6040096 Measuring thermal expansion of mask substrate loosely supported to allow free thermal expansion, adjusting alignment of the mask substrate and the photosensitive substrate in response to the expansion amount |
| 03/21/2000 | US6040095 Mask having measurement marks throughout the area of an e-beam projection mask on a grid of struts extending between sub-field membrane mask areas, the marks having been applied concurrently with patterning sub-field membrane mask areas |