Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2000
03/28/2000US6043552 Semiconductor device and method of manufacturing the semiconductor device
03/28/2000US6043547 Circuit structure with an anti-reflective layer
03/28/2000US6043546 Planar channel-type MOS transistor
03/28/2000US6043545 MOSFET device with two spacers
03/28/2000US6043544 Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric
03/28/2000US6043543 Read-only memory cell configuration with trench MOS transistor and widened drain region
03/28/2000US6043541 Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits
03/28/2000US6043540 Static RAM having cell transistors with longer gate electrodes than transistors in the periphery of the cell
03/28/2000US6043538 Device structure for high voltage tolerant transistor on a 3.3 volt process
03/28/2000US6043537 Embedded memory logic device using self-aligned silicide and manufacturing method therefor
03/28/2000US6043536 Semiconductor device
03/28/2000US6043535 Self-aligned implant under transistor gate
03/28/2000US6043534 High voltage semiconductor device
03/28/2000US6043533 Method of integrating Ldd implantation for CMOS device fabrication
03/28/2000US6043531 Method for producing bridged, doped zones
03/28/2000US6043530 Flash EEPROM device employing polysilicon sidewall spacer as an erase gate
03/28/2000US6043529 Semiconductor configuration with a protected barrier for a stacked cell
03/28/2000US6043528 Semiconductor memory device having trench-type capacitor structure using high dielectric film and its manufacturing method
03/28/2000US6043526 Semiconductor memory cell using a ferroelectric thin film and a method for fabricating it
03/28/2000US6043522 Field effect transistor array including doped two-cell isolation region for preventing latchup
03/28/2000US6043521 Layout pattern of memory cell circuit
03/28/2000US6043520 Gallium arsenide (gaas) ballast resistor layer is provided in a heterojunction bipolar transistor having gaas emitter layer, indium galium phosphide spacer layer and gaas base layer, controls ballast resistance
03/28/2000US6043519 Junction high electron mobility transistor-heterojunction bipolar transistor (JHEMT-HBT) monolithic microwave integrated circuit (MMIC) and single growth method of fabrication
03/28/2000US6043516 Semiconductor component with scattering centers within a lateral resistor region
03/28/2000US6043513 Silicon carbide overcoated with aluminum titanium silicide (sic) layer, with ohmic contact comprising aluminum titanium silicide on the sic layer; ohmic contact has low specific contact resistance and is stable over wide temperature range
03/28/2000US6043512 Thin film semiconductor device and method for producing the same
03/28/2000US6043511 Thin film transistor array panel used for a liquid crystal display having patterned data line components
03/28/2000US6043508 Photodetector involving a MOSFET having a floating gate
03/28/2000US6043502 Apparatus and method for sensing an insertion state of a wafer in a cassette
03/28/2000US6043500 Exposure apparatus and its control method
03/28/2000US6043460 System and method for thermal processing of a semiconductor substrate
03/28/2000US6043458 Pneumatic rotatable hand held pickup tool
03/28/2000US6043453 Apparatus for laser processing with a mechanical cutter
03/28/2000US6043450 Method to compensate for non-uniform film growth during chemical vapor deposition
03/28/2000US6043437 Alumina insulation for coating implantable components and other microminiature devices
03/28/2000US6043436 Wiring structure having rotated wiring layers
03/28/2000US6043429 Method of making flip chip packages
03/28/2000US6043330 Synthesis of siloxane resins
03/28/2000US6043206 Water, fluoroboric acid, a surfactant, and phosphoric acid.
03/28/2000US6043167 Method for forming low dielectric constant insulating film
03/28/2000US6043166 Implanting oxygen under two conditions and performing two high temperature anneals at temperatures above 1250 degrees c. and above 1300 degrees c., respectively, at two respective oxygen concentrations.
03/28/2000US6043165 Methods of forming electrically interconnected lines using ultraviolet radiation as an organic compound cleaning agent
03/28/2000US6043164 Method for transferring a multi-level photoresist pattern
03/28/2000US6043163 HCL in overetch with hard mask to improve metal line etching profile
03/28/2000US6043162 Contamination on semiconductor wafers in vapor phase etching is eliminated by performing the drying step quickly, thereby improving productivity.
03/28/2000US6043160 Method of manufacturing a monitor pad for chemical mechanical polishing planarization
03/28/2000US6043159 Chemical mechanical polishing process for layers of isolating materials based on silicon derivatives or silicon
03/28/2000US6043158 Semiconductor device with contact holes differing in depth and manufacturing method thereof
03/28/2000US6043157 Semiconductor device having dual gate electrode material and process of fabrication thereof
03/28/2000US6043156 Method of making semiconductor wafers
03/28/2000US6043155 Polishing agent and polishing method
03/28/2000US6043154 Utilizes the tendency for implanted phosphorus ions in a hemispherical grain polysilicon layer to gather near the grooves so that the rate of oxidation there increases.
03/28/2000US6043153 Method for reducing electromigration in a copper interconnect
03/28/2000US6043152 Method to reduce metal damage in the HDP-CVD process by using a sacrificial dielectric film
03/28/2000US6043150 Method for uniform plating of dendrites
03/28/2000US6043149 Method of purifying a metal line in a semiconductor device
03/28/2000US6043148 Method of fabricating contact plug
03/28/2000US6043147 Method of prevention of degradation of low dielectric constant gap-fill material
03/28/2000US6043146 Process for forming a semiconductor device
03/28/2000US6043145 Method for making multilayer wiring structure
03/28/2000US6043143 Ohmic contact and method of manufacture
03/28/2000US6043142 Semiconductor apparatus having conductive thin films and manufacturing apparatus therefor
03/28/2000US6043141 Forming a lattice comprising hg and a group vi material wherein a cation-rich condition is established at the surface; generating an elemental group v flux by evaporating an elemental group v material
03/28/2000US6043140 Method for growing a nitride compound semiconductor
03/28/2000US6043139 Process for controlling dopant diffusion in a semiconductor layer
03/28/2000US6043138 Multi-step polysilicon deposition process for boron penetration inhibition
03/28/2000US6043137 Getter pump module and system
03/28/2000US6043136 Silicon oxide layer is formed through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition method employing an ozone oxidant and a teos silicon source
03/28/2000US6043135 Process of fabricating a semiconductor device having trench isolation allowing pattern image to be exactly transferred to photo-resist layer extending thereon
03/28/2000US6043134 Semiconductor wafer alignment processes
03/28/2000US6043133 Method of photo alignment for shallow trench isolation chemical-mechanical polishing
03/28/2000US6043132 Method for forming HSG silicon film of semiconductor device
03/28/2000US6043131 Method for making a flower shaped DRAM capacitor
03/28/2000US6043130 Process for forming bipolar transistor compatible with CMOS utilizing tilted ion implanted base
03/28/2000US6043129 High density MOSFET with raised source and drain regions
03/28/2000US6043128 Semiconductor device handling multi-level voltages
03/28/2000US6043127 Method for manufacturing multiple stage ROM unit
03/28/2000US6043126 Process for manufacture of MOS gated device with self aligned cells
03/28/2000US6043125 Method of fabricating vertical power MOSFET having low distributed resistance
03/28/2000US6043124 Method for forming high density nonvolatile memories with high capacitive-coupling ratio
03/28/2000US6043123 Triple well flash memory fabrication process
03/28/2000US6043122 Three-dimensional non-volatile memory
03/28/2000US6043121 Method for fabricating an one-time programmable read only memory
03/28/2000US6043120 Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation
03/28/2000US6043119 Method of making a capacitor
03/28/2000US6043118 Semiconductor memory circuit device and method for fabricating a semiconductor memory device circuit
03/28/2000US6043117 SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and method of making
03/28/2000US6043116 Method of fabricating self-align-contact
03/28/2000US6043115 Method for avoiding interference in a CMOS sensor
03/28/2000US6043114 Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device
03/28/2000US6043113 Method of forming self-aligned thin film transistor
03/28/2000US6043112 IGBT with reduced forward voltage drop and reduced switching loss
03/28/2000US6043111 Small size semiconductor package
03/28/2000US6043106 Method for surface passivation and protection of cadmium zinc telluride crystals
03/28/2000US6043105 Method for manufacturing semiconductor sensitive devices
03/28/2000US6043102 Assessing plasma induced gate dielectric degradation with stress induced leakage current measurements
03/28/2000US6043100 Chip on tape die reframe process
03/28/2000US6043005 A 2-pyrrolidinone; lactic acid; and a peroxide wherein the peroxide is hydrogen peroxide or a peroxycarboxylic acid.
03/28/2000US6043004 Ashing method
03/28/2000US6043003 E-beam application to mask making using new improved KRS resist system