Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2000
12/05/2000US6156639 Method for manufacturing contact structure
12/05/2000US6156638 Integrated circuitry and method of restricting diffusion from one material to another
12/05/2000US6156637 Method of planarizing a semiconductor device by depositing a dielectric ply structure
12/05/2000US6156636 Method of manufacturing a semiconductor device having self-aligned contact holes
12/05/2000US6156635 Method of correcting solder bumps
12/05/2000US6156634 Forming refractory metal oxide layer on substrate; performing hydrogen treatment after formation of refractory metal oxide layer to improve conductivity of metal oxide layer
12/05/2000US6156633 Process for forming high temperature stable self-aligned metal silicide layer
12/05/2000US6156632 Method of forming polycide structures
12/05/2000US6156631 Depositing conductive layer over uneven substrate; depositing silicon nitride buffer layer; planarizing surface of buffer layer; selectively removing buffer to form mask pattern; removing conductive layer according to mask pattern
12/05/2000US6156630 Titanium boride gate electrode and interconnect and methods regarding same
12/05/2000US6156629 Method for patterning a polysilicon gate in deep submicron technology
12/05/2000US6156628 Semiconductor device and method of manufacturing the same
12/05/2000US6156627 Method of promoting crystallization of an amorphous semiconductor film using organic metal CVD
12/05/2000US6156626 Electromigration bonding process and system
12/05/2000US6156625 Partial semiconductor wafer processing using wafermap display
12/05/2000US6156624 Preparing silicon substrates with silicon dioxide surfaces; treating to form hydrophobic silicon surface; joining substrates; heat treating; removing part of substratre to sandwitch silicon dioxide layer
12/05/2000US6156623 Stress control of thin films by mechanical deformation of wafer substrate
12/05/2000US6156622 Bipolar transistor having isolation regions
12/05/2000US6156621 Method for fabricating direct wafer bond Si/SiO2 /Si substrates
12/05/2000US6156620 Forming isolation trench in silicon semiconductor substrate; forming barrier region by treating with nitrogen; forming silicon oxide layer over barrier to confine nitrogen in barrier region
12/05/2000US6156619 Semiconductor device and method of fabricating
12/05/2000US6156618 Method for fabricating thin film resistor
12/05/2000US6156617 Method of manufacturing semiconductor device
12/05/2000US6156616 Method for fabricating an NPN transistor in a BICMOS technology
12/05/2000US6156615 Method for decreasing the contact resistance of silicide contacts by retrograde implantation of source/drain regions
12/05/2000US6156613 Method to form MOSFET with an elevated source/drain
12/05/2000US6156612 Methods of forming field oxide and active area regions on a semiconductive substrate
12/05/2000US6156611 Method of fabricating vertical FET with sidewall gate electrode
12/05/2000US6156610 Process for manufacturing an EEPROM having a peripheral transistor with thick oxide
12/05/2000US6156609 EEPROM device manufacturing method
12/05/2000US6156608 Method of manufacturing cylindrical shaped capacitor
12/05/2000US6156607 Method for a folded bit line memory using trench plate capacitor cells with body bias contacts
12/05/2000US6156606 Providing deep trench in substrate, deep trench having lower portion; forming dielectric layer in deep trench by lining lower portion of deep trench with the dielectric layer, the dielectric layer including rutile titanuium dioxide layer
12/05/2000US6156605 Method of fabricating DRAM device
12/05/2000US6156604 Method for making an open bit line memory cell with a vertical transistor and trench plate trench capacitor
12/05/2000US6156603 Manufacturing method for reducing the thickness of a dielectric layer
12/05/2000US6156602 Self-aligned precise high sheet RHO register for mixed-signal application
12/05/2000US6156601 Method of forming DRAM matrix of basic organizational units each with pair of capacitors with hexagon shaped planar portion
12/05/2000US6156600 Method for fabricating capacitor in integrated circuit
12/05/2000US6156599 Forming dielectric metal oxide on electrode on substrate; forming second electrode on dielectric; where electrode(s) formed from metal still conductive when oxidized, by reacting with less than stoichiometric amount of oxygen; nonsiliciding
12/05/2000US6156598 Method for forming a lightly doped source and drain structure using an L-shaped spacer
12/05/2000US6156597 Additional buffer layer for eliminating ozone/tetraethylorthosilicate sensitivity on an arbitrary trench structure
12/05/2000US6156596 Method for fabricating a complementary metal oxide semiconductor image sensor
12/05/2000US6156595 Method of fabricating a Bi-CMOS IC device including a self-alignment bipolar transistor capable of high speed operation
12/05/2000US6156594 Fabrication of bipolar/CMOS integrated circuits and of a capacitor
12/05/2000US6156593 Method for fabricating salicide CMOS and non-salicide electrostatic discharge protection circuit in a single chip
12/05/2000US6156592 Method of manufacturing a semiconductor device containing CMOS elements
12/05/2000US6156591 Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts
12/05/2000US6156590 Method for producing semiconductor device
12/05/2000US6156589 Compact SOI body contact link
12/05/2000US6156584 Method of manufacturing a semiconductor light emitting device
12/05/2000US6156583 Method for manufacturing a liquid crystal display device
12/05/2000US6156582 Method of fabricating top emitting ridge VCSEL with self-aligned contact and sidewall reflector
12/05/2000US6156581 Reacting a vapor-phase gallium aluminum indium composition with a vapor-phase nitrogenous compound in the presence of a substrate to grow a gallium aluminum indium nitride base layer on the substrate, thereby yielding a microelectronic device
12/05/2000US6156580 Semiconductor wafer analysis system and method
12/05/2000US6156485 Using tungsten hardmask with selectivity to the underlying aluminum-copper metal layer; to protect lithographic integrity, overlying organic bottom antireflective coating prevents reflections from the hardmask and underlying metal
12/05/2000US6156476 Positive photoresist composition
12/05/2000US6156474 An alkali-soluble novolak resin, a quinonediazide group-containing compound, and to improve adhesion to a substrate, an n,n,n',n'-tetrakis(ethylene oxide-propylene oxide block polymer) ethylene diamine specified compound
12/05/2000US6156464 Scanning-type charged-particle beam exposure methods including scan-velocity error detection and correction
12/05/2000US6156463 One-step determination of minimum amount of the exposure for removing a photoresist film by irradiating light through a photomask having openings with varying transmittance values; determing etching rate; semiconductors; integrated circuits
12/05/2000US6156461 Method for repair of photomasks
12/05/2000US6156460 A quartz glass substrate having a clear area, a gray area of a deep uv-light-absorbing amorphous silicon layer through which incident light is partly transmitted and a dark area of light-blocking chromium film; interconnections and vias
12/05/2000US6156445 A metallized ceramic substrate coated a film of an ablatively photodecomposable acrylate polymer modified by disperse red 1, a photoabsorber; circuit patterns; no phase separation or crystallization, even ablation and high resolution
12/05/2000US6156435 Formed by monomer gas pyrolysis and plasma excitation methods; can be carried out individually, sequentially, or simultaneously to produce flexible fluorocarbon polymer thin films on wires, twisted wires, tubes, complex microstructures
12/05/2000US6156423 Base material having film layer which is a radiation cured mixture of urethane (meth) acrylate oligomer and reactive-diluted monomer, and barrier layer on one surface of film layer and adhesive layer on one surface
12/05/2000US6156414 Carrier film and process for producing the same
12/05/2000US6156408 Device for reworkable direct chip attachment
12/05/2000US6156393 Method of molecular-scale pattern imprinting at surfaces
12/05/2000US6156382 Vapor deposition of a thin nucleating film using a tungsten source/reducing agent gas mixture, treating substrate in a group iii or v hydride ambient without tungsten, then adding tungsten source and second reducing agent for bulk deposition
12/05/2000US6156374 Method of forming insulating material between components of an integrated circuit
12/05/2000US6156217 Method for the purpose of producing a stencil mask
12/05/2000US6156171 Sputtering magnetron
12/05/2000US6156167 Clamshell apparatus for electrochemically treating semiconductor wafers
12/05/2000US6156165 Enclosing integrated circuit chip in a mask which exposes an area on an edge of integrated circuit chip and areas on major surfaces of the integrated circuit chip contiguous to area on edge of integrated circuit chip, applying metal
12/05/2000US6156153 Chemical treatment apparatus and chemical treatment method
12/05/2000US6156152 Plasma processing apparatus
12/05/2000US6156149 In situ deposition of a dielectric oxide layer and anti-reflective coating
12/05/2000US6156126 Exposing to volatile solvent
12/05/2000US6156125 Adhesion apparatus
12/05/2000US6156124 Wafer transfer station for a chemical mechanical polisher
12/05/2000US6156122 Depositor for depositing a dielectric layer with fewer metallic impurities and a method for reducing the content of the metallic impurities in the dielectric layer by using this depositor
12/05/2000US6156121 Wafer boat and film formation method
12/05/2000US6156105 Semiconductor manufacturing system with getter safety device
12/05/2000US6156079 Radiation passageway
12/05/2000US6156078 Testing and finishing apparatus for integrated circuit package units
12/05/2000US6155909 Controlled cleavage system using pressurized fluid
12/05/2000US6155908 Work-loading method and surface-grinding apparatus with work position deviation-adjusting mechanism
12/05/2000US6155773 Substrate clamping apparatus
12/05/2000US6155768 Multiple link robot arm system implemented with offset end effectors to provide extended reach and enhanced throughput
12/05/2000US6155716 Guide apparatus for biaxial shifting motion and uniaxial turning motion
12/05/2000US6155542 Vibration damping apparatus and method
12/05/2000US6155540 Apparatus for vaporizing and supplying a material
12/05/2000US6155537 Deep submicron MOS transistors with a self-aligned gate electrode
12/05/2000US6155436 Arc inhibiting wafer holder assembly
12/05/2000US6155426 Cassette case for holding substrates therein
12/05/2000US6155275 Substrate processing unit and substrate processing apparatus using the same
12/05/2000US6155247 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions
12/05/2000US6155203 Apparatus for control of deposit build-up on an inner surface of a plasma processing chamber
12/05/2000US6155201 Plasma processing apparatus and plasma processing method
12/05/2000US6155199 Parallel-antenna transformer-coupled plasma generation system
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