Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2000
12/06/2000CN1275799A Method for making semiconductor device
12/06/2000CN1275798A Long-wave electricity-limiting adjustable infrared pick-up target
12/06/2000CN1275797A Electronic beam explosure mask and method for making semiconductor device with same
12/06/2000CN1275796A Method for making semiconductor device
12/06/2000CN1275795A Equipment for processing chip
12/06/2000CN1275761A Magnet head, magnetic disk, and connection method and equipment
12/06/2000CN1275634A Vacuum chamber for plain substrate
12/06/2000CN1275484A Picture composition method, device, template and method for making same
12/06/2000CN1275418A Method for removing inpurity from fluid
12/06/2000CN1275417A Method for removing removed substance from fluid
12/06/2000CN1275416A Apparatus for removing removed substance from fluid
12/06/2000CN1059290C Method for assembly integrated circuit on a shared substrate
12/06/2000CN1059278C Process for manufacturing optical shade of zero level of integrated circuit
12/06/2000CN1059219C Polymeric substrate containing polymeric microelements and method of making and using the same
12/05/2000US6157900 Knowledge based system and method for determining material properties from fabrication and operating parameters
12/05/2000US6157866 Automated material handling system for a manufacturing facility divided into separate fabrication areas
12/05/2000US6157774 Vapor generating method and apparatus using same
12/05/2000US6157588 Semiconductor memory device having hierarchical word line structure
12/05/2000US6157583 Integrated circuit memory having a fuse detect circuit and method therefor
12/05/2000US6157580 Semiconductor memory device capable of easily controlling a reference ratio regardless of change of a process parameter
12/05/2000US6157575 Nonvolatile memory device and operating method thereof
12/05/2000US6157568 Avalanche programmed floating gate memory cell structure with program element in first polysilicon layer
12/05/2000US6157564 Semiconductor device
12/05/2000US6157561 Integrated circuit memory with low resistance, segmented power supply lines
12/05/2000US6157492 Apparatus and method for laser radiation
12/05/2000US6157452 Position detecting apparatus
12/05/2000US6157451 Sample CD measurement system
12/05/2000US6157421 Liquid crystal display and method of manufacturing the same
12/05/2000US6157249 Semiconductor integrated circuit with reduced device and interconnection areas
12/05/2000US6157240 Output logic setting circuit in semiconductor integrated circuit
12/05/2000US6157230 Method for realizing an improved radio frequency detector for use in a radio frequency identification device, frequency lock loop, timing oscillator, method of constructing a frequency lock loop and method of operating an integrated circuit
12/05/2000US6157216 Circuit driver on SOI for merged logic and memory circuits
12/05/2000US6157207 Protection of logic modules in a field programmable gate array during antifuse programming
12/05/2000US6157203 Input circuit with improved operating margin using a single input differential circuit
12/05/2000US6157202 Hybrid IC with circuit for burn-in test
12/05/2000US6157199 Method of monitoring ion-implantation process using photothermal response from ion-implanted sample, and monitoring apparatus of ion-implantation process
12/05/2000US6157159 Stage system and exposure apparatus using the same
12/05/2000US6157106 Magnetically-levitated rotor system for an RTP chamber
12/05/2000US6157087 Consistent alignment mark profiles on semiconductor wafers using metal organic chemical vapor deposition titanium nitride protective layer
12/05/2000US6157086 Chip package with transfer mold underfill
12/05/2000US6157085 Semiconductor device for preventing exfoliation from occurring between a semiconductor chip and a resin substrate
12/05/2000US6157083 Fluorine doping concentrations in a multi-structure semiconductor device
12/05/2000US6157082 Semiconductor device having aluminum contacts or vias and method of manufacture therefor
12/05/2000US6157081 High-reliability damascene interconnect formation for semiconductor fabrication
12/05/2000US6157080 Semiconductor device using a chip scale package
12/05/2000US6157079 Semiconductor device with a bump including a bump electrode film covering a projecting photoresist
12/05/2000US6157078 Reduced variation in interconnect resistance using run-to-run control of chemical-mechanical polishing during semiconductor fabrication
12/05/2000US6157077 Semiconductor device with plated heat sink and partially plated side surfaces
12/05/2000US6157073 Isolation between power supplies of an analog-digital circuit
12/05/2000US6157069 Highly integrated mask ROM for coding data
12/05/2000US6157068 Semiconductor device with local interconnect of metal silicide
12/05/2000US6157067 Metal oxide semiconductor capacitor utilizing dummy lithographic patterns
12/05/2000US6157064 Method and a deep sub-micron field effect transistor structure for suppressing short channel effects
12/05/2000US6157063 MOS field effect transistor with an improved lightly doped diffusion layer structure and method of forming the same
12/05/2000US6157062 Integrating dual supply voltage by removing the drain extender implant from the high voltage device
12/05/2000US6157061 Nonvolatile semiconductor memory device and method of manufacturing the same
12/05/2000US6157060 High density integrated semiconductor memory and method for producing the memory
12/05/2000US6157059 Nonvolatile floating gate memory with improved interpoly dielectric
12/05/2000US6157058 Low voltage EEPROM/NVRAM transistors and making method
12/05/2000US6157057 Flash memory cell
12/05/2000US6157056 Semiconductor memory device having a plurality of memory cell transistors arranged to constitute memory cell arrays
12/05/2000US6157055 Semiconductor memory device having a long data retention time with the increase in leakage current suppressed
12/05/2000US6157053 Charge transfer device and method of driving the same
12/05/2000US6157052 Semiconductor integrated circuit having three wiring layers
12/05/2000US6157039 Charged particle beam illumination of blanking aperture array
12/05/2000US6157003 Furnace for processing semiconductor wafers
12/05/2000US6156997 Laser processing method and laser processing apparatus
12/05/2000US6156980 Flip chip on circuit board with enhanced heat dissipation and method therefor
12/05/2000US6156968 Solar cell, a method of producing the same and a semiconductor producing apparatus
12/05/2000US6156676 Laser marking of semiconductor wafer substrate while inhibiting adherence to substrate surface of particles generated during laser marking
12/05/2000US6156675 Method for enhanced dielectric film uniformity
12/05/2000US6156674 Semiconductor processing methods of forming insulative materials
12/05/2000US6156673 Process for producing a ceramic layer
12/05/2000US6156672 Method of forming dielectric thin film pattern and method of forming laminate pattern comprising dielectric thin film and conductive thin film
12/05/2000US6156671 Method for improving characteristic of dielectric material
12/05/2000US6156668 Sequentially forming etched layer and photosensitive film for silylation on semiconductor substrates; exposing; forming silylation region; etching
12/05/2000US6156666 Etching nickel film on substrate by plasma gas generated by ethching gas containing carbon monoxide and/or carbondioxide, cooling while substrate is being etched
12/05/2000US6156665 Depositing photoresist layer of polymer on semiconductor substrate; depositing intermeidate layer of silicon oxide by electron beam evaporation; patterning by lithography; transferring metallization pattern; removing
12/05/2000US6156664 Method of manufacturing liner insulating layer
12/05/2000US6156663 Method and apparatus for plasma processing
12/05/2000US6156662 Fabrication process of a liquid crystal display device with improved yield
12/05/2000US6156661 Post clean treatment
12/05/2000US6156660 Method of planarization using dummy leads
12/05/2000US6156658 Depositing ultra-thin photoresist over silicon layer; irradiating with electromagnetic radiation; developing photoresist to expose silicon layer; etching silicon layer to expose oxide layer, etching oxide to expose metal layer
12/05/2000US6156656 Process for manufacturing a semiconductor device
12/05/2000US6156655 Depositing dielectric layer on substrate to cover metal line; forming opening; forming laminated layer; forming copper layer; removing copper layer and laminated layer outside opening to form damascene; forming second laminated layer
12/05/2000US6156654 Providing metal-oxide semiconductor field-effect structures on silicon wafer and selective epitaxial growth of silicon; cleaning wafer with diluted hf or in-situ back-sputter with argon; sputter depositing titanium and titanium nitride layer
12/05/2000US6156653 Method of fabricating a MOS device
12/05/2000US6156651 Metallization method for porous dielectrics
12/05/2000US6156650 Method of releasing gas trapped during deposition
12/05/2000US6156649 Method of forming uniform sheet resistivity salicide
12/05/2000US6156648 Method for fabricating dual damascene
12/05/2000US6156647 Barrier layer structure which prevents migration of silicon into an adjacent metallic layer and the method of fabrication of the barrier layer
12/05/2000US6156646 Method of manufacturing semiconductor devices
12/05/2000US6156645 Method of forming a metal layer on a substrate, including formation of wetting layer at a high temperature
12/05/2000US6156644 Method for forming interconnects for semiconductor devices using reaction control layers, and interconnects formed thereby
12/05/2000US6156643 Method of forming a dual damascene trench and borderless via structure
12/05/2000US6156642 Method of fabricating a dual damascene structure in an integrated circuit
12/05/2000US6156641 Semiconductor processing methods of forming self-aligned contact openings
12/05/2000US6156640 Damascene process with anti-reflection coating
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