Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2000
12/12/2000US6159861 Method of manufacturing semiconductor device
12/12/2000US6159860 Method for etching layers on a semiconductor wafer in a single etching chamber
12/12/2000US6159859 Gas phase removal of SiO2 /metals from silicon
12/12/2000US6159858 Slurry containing manganese oxide and a fabrication process of a semiconductor device using such a slurry
12/12/2000US6159857 Robust post Cu-CMP IMD process
12/12/2000US6159856 Method of manufacturing a semiconductor device with a silicide layer
12/12/2000US6159855 Multi-metallic mixtures of metalloamide compounds.
12/12/2000US6159854 Process of growing conductive layer from gas phase
12/12/2000US6159853 Method for using ultrasound for assisting forming conductive layers on semiconductor devices
12/12/2000US6159852 Method of depositing polysilicon, method of fabricating a field effect transistor, method of forming a contact to a substrate, method of forming a capacitor
12/12/2000US6159851 Borderless vias with CVD barrier layer
12/12/2000US6159850 Method for reducing resistance of contact window
12/12/2000US6159849 Methods of forming nitride dielectric layers having reduced exposure to oxygen
12/12/2000US6159848 Method of manufacturing a semiconductor device having a high melting point metal film
12/12/2000US6159847 Alcu alloys with higher cu content are added in thin layers within a metallization structure.
12/12/2000US6159846 Method of metallization in semiconductor devices
12/12/2000US6159845 Method for manufacturing dielectric layer
12/12/2000US6159844 Fabrication of gate and diffusion contacts in self-aligned contact process
12/12/2000US6159843 Method of fabricating landing pad
12/12/2000US6159842 Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections
12/12/2000US6159841 Method of fabricating lateral power MOSFET having metal strap layer to reduce distributed resistance
12/12/2000US6159840 Fabrication method for a dual damascene comprising an air-gap
12/12/2000US6159839 Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections
12/12/2000US6159837 Manufacturing method of semiconductor device
12/12/2000US6159835 Encapsulated low resistance gate structure and method for forming same
12/12/2000US6159834 Method of forming a gate quality oxide-compound semiconductor structure
12/12/2000US6159833 Method of forming a contact hole in a semiconductor wafer
12/12/2000US6159832 Precision laser metallization
12/12/2000US6159830 Process for adjusting the carrier lifetime in a semiconductor component
12/12/2000US6159829 Memory device using movement of protons
12/12/2000US6159828 Semiconductor processing method of providing a doped polysilicon layer
12/12/2000US6159827 Preparation process of semiconductor wafer
12/12/2000US6159826 Semiconductor wafer and fabrication method of a semiconductor chip
12/12/2000US6159825 Controlled cleavage thin film separation process using a reusable substrate
12/12/2000US6159824 Low-temperature bonding process maintains the integrity of a layer of microbubbles; high-temperature annealing process finishes the bonding process of the thin film to the target wafer
12/12/2000US6159823 Trench isolation method of semiconductor device
12/12/2000US6159822 Self-planarized shallow trench isolation
12/12/2000US6159821 Methods for shallow trench isolation
12/12/2000US6159820 Method for fabricating a DRAM cell capacitor
12/12/2000US6159819 Fabrication of capacitors with low voltage coefficient of capacitance
12/12/2000US6159818 Method of forming a container capacitor structure
12/12/2000US6159817 Multi-tap thin film inductor
12/12/2000US6159816 Method of fabricating a bipolar transistor
12/12/2000US6159815 Method of producing a MOS transistor
12/12/2000US6159814 Spacer formation by poly stack dopant profile design
12/12/2000US6159813 Graded LDD implant process for sub-half-micron MOS devices
12/12/2000US6159812 Reduced boron diffusion by use of a pre-anneal
12/12/2000US6159811 Methods for patterning microelectronic structures using chlorine, oxygen, and fluorine
12/12/2000US6159810 Methods of fabricating gates for integrated circuit field effect transistors including amorphous impurity layers
12/12/2000US6159809 Method for manufacturing surface channel type P-channel MOS transistor while suppressing P-type impurity penetration
12/12/2000US6159808 Method of forming self-aligned DRAM cell
12/12/2000US6159807 Self-aligned dynamic threshold CMOS device
12/12/2000US6159806 Method for increasing the effective spacer width
12/12/2000US6159805 Semiconductor electronic device with autoaligned polysilicon and silicide control terminal
12/12/2000US6159804 Disposable sidewall oxidation fabrication method for making a transistor having an ultra short channel length
12/12/2000US6159803 Method of fabricating flash memory
12/12/2000US6159802 Method of forming a stack-gate of a non-volatile memory on a semiconductor wafer
12/12/2000US6159801 Method to increase coupling ratio of source to floating gate in split-gate flash
12/12/2000US6159800 Method of forming a memory cell
12/12/2000US6159799 Method of manufacturing semiconductor device comprising high voltage regions and floating gates
12/12/2000US6159798 Method for forming a floating gate with improved surface roughness
12/12/2000US6159797 Method of fabricating a flash memory with a planarized topography
12/12/2000US6159796 Method of forming a non-volatile memory cell having a high coupling capacitance including forming an insulator mask, etching the mask, and forming a u-shaped floating gate
12/12/2000US6159795 Low voltage junction and high voltage junction optimization for flash memory
12/12/2000US6159794 Methods for removing silicide residue in a semiconductor device
12/12/2000US6159793 Structure and fabricating method of stacked capacitor
12/12/2000US6159792 Method for forming a capacitor of semiconductor device
12/12/2000US6159791 Fabrication method of capacitor
12/12/2000US6159790 Method of controlling outdiffusion in doped three-dimensional film by using angled implants
12/12/2000US6159789 Method for fabricating capacitor
12/12/2000US6159788 Method to increase DRAM cell capacitance
12/12/2000US6159787 Structures and processes for reduced topography trench capacitors
12/12/2000US6159786 Well-controlled CMP process for DRAM technology
12/12/2000US6159785 Semiconductor device and manufacturing method thereof
12/12/2000US6159784 Method of producing semiconductor device
12/12/2000US6159783 Semiconductor device having MOS transistor and method of manufacturing the same
12/12/2000US6159782 Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant
12/12/2000US6159781 Way to fabricate the self-aligned T-shape gate to reduce gate resistivity
12/12/2000US6159780 Method of fabricating semiconductor device on SOI substrate
12/12/2000US6159779 Multi-layer gate for TFT and method of fabrication
12/12/2000US6159778 Methods of forming semiconductor-on-insulator field effect transistors with reduced floating body parasitics
12/12/2000US6159777 Method of forming a TFT semiconductor device
12/12/2000US6159776 Method for manufacturing semiconductor device
12/12/2000US6159773 Strain release contact system for integrated circuits
12/12/2000US6159772 Packaging electrical circuits
12/12/2000US6159770 Method and apparatus for fabricating semiconductor device
12/12/2000US6159769 Use of palladium in IC manufacturing
12/12/2000US6159766 Designing method of leadframe tip arrangement
12/12/2000US6159765 Integrated circuit package having interchip bonding and method therefor
12/12/2000US6159763 Method and device for forming semiconductor thin film, and method and device for forming photovoltaic element
12/12/2000US6159756 Method of testing semiconductor device
12/12/2000US6159755 Method and system for detecting faults in a flip-chip package
12/12/2000US6159754 Polyimide layer acts as both an insulation layer and an anti-reflective coating layer.
12/12/2000US6159753 Method and apparatus for editing an integrated circuit
12/12/2000US6159752 Method of forming para-dielectric and ferro-dielectric capacitors over a silicon substrate
12/12/2000US6159665 Processes using photosensitive materials including a nitro benzyl ester photoacid generator
12/12/2000US6159663 Ion vapor depositing an aluminum containing mixture on the member, covering with a photoresist layer, photolithographic process, coating a metal corrosion inhibiting layer, electroless plating
12/12/2000US6159661 Dual damascene process
12/12/2000US6159660 Opposite focus control to avoid keyholes inside a passivation layer
12/12/2000US6159655 Positive photoresist composition for exposure to far ultraviolet light
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