Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2000
11/15/2000CN1058585C Semiconductor device
11/15/2000CN1058584C Semiconductor device and fabrication method of the same
11/15/2000CN1058583C Semconductor and process for fabricating the same
11/15/2000CN1058467C Apparatus for transporting lead frame and in-line chips bonding equipment and method for manufacturing semiconductor chip
11/14/2000US6148434 Apparatus and method for minimizing the delay times in a semiconductor device
11/14/2000US6148307 Method and system for generating product performance history
11/14/2000US6148276 Diffusion simulating method
11/14/2000US6148246 Semiconductor process system, its control method, computer readable memory, and device manufacturing method
11/14/2000US6148099 Method and apparatus for incremental concurrent learning in automatic semiconductor wafer and liquid crystal display defect classification
11/14/2000US6147922 Non-volatile storage latch
11/14/2000US6147917 Apparatus and method for noise reduction in DRAM
11/14/2000US6147914 On-chip word line voltage generation for DRAM embedded in logic process
11/14/2000US6147884 Method and apparatus for low-power charge transition in an I/O system of an integrated circuit
11/14/2000US6147876 Multi-chip module having printed wiring board comprising circuit pattern for IC chip
11/14/2000US6147853 Protection circuit that can be associated with a filter
11/14/2000US6147852 Device for protecting an integrated circuit against electrostatic discharges
11/14/2000US6147745 Exposure apparatus
11/14/2000US6147739 Drive IC, liquid crystal panel, liquid crystal device, and electronic apparatus
11/14/2000US6147667 Semiconductor device
11/14/2000US6147556 Solid-state image sensor
11/14/2000US6147546 Zero volt/zero current fuse arrangement
11/14/2000US6147520 Integrated circuit having controlled impedance
11/14/2000US6147511 Overvoltage-tolerant interface for integrated circuits
11/14/2000US6147509 Semiconductor logical device capable of circuit switching without being influenced by transitional effects
11/14/2000US6147413 Mask repattern process
11/14/2000US6147409 Modified multilayered metal line structure for use with tungsten-filled vias in integrated circuit structures
11/14/2000US6147408 Method of forming embedded copper interconnections and embedded copper interconnection structure
11/14/2000US6147407 Article comprising fluorinated amorphous carbon and process for fabricating article
11/14/2000US6147406 Electrical connection between an electrically conductive line and a node location, and integrated circuitry
11/14/2000US6147404 Dual barrier and conductor deposition in a dual damascene process for semiconductors
11/14/2000US6147403 Reduced wafer warping of semiconductor wafers without weakening the strength of adhesion to substrate materials; aluminum, titanium, silicon, titanium nitride layers
11/14/2000US6147402 Refractory metal capped low resistivity metal conductor lines and vias
11/14/2000US6147401 Compliant multichip package
11/14/2000US6147400 Connecting multiple microelectronic elements with lead deformation
11/14/2000US6147398 Semiconductor device package
11/14/2000US6147397 Stress isolated integrated circuit and method for making
11/14/2000US6147394 Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby
11/14/2000US6147393 Isolated multi-chip devices
11/14/2000US6147388 Polycide gate structure with intermediate barrier
11/14/2000US6147387 Static random access memory
11/14/2000US6147386 Semiconductor device and method of producing the same
11/14/2000US6147385 CMOS static random access memory devices
11/14/2000US6147384 Method for forming planar field effect transistors with source and drain an insulator and device constructed therefrom
11/14/2000US6147383 LDD buried channel field effect semiconductor device and manufacturing method
11/14/2000US6147380 Floating gate non-volatile memory cell with low erasing voltage and having different potential barriers
11/14/2000US6147379 Semiconductor device and method for fabricating the same
11/14/2000US6147378 Fully recessed semiconductor device and method for low power applications with single wrap around buried drain region
11/14/2000US6147377 Fully recessed semiconductor device
11/14/2000US6147376 DRAM cell arrangement and method for its production
11/14/2000US6147375 Active matrix display device
11/14/2000US6147371 Bipolar transistor and manufacturing method for same
11/14/2000US6147370 Field effect transistor with first and second drain electrodes
11/14/2000US6147362 High performance display pixel for electronics displays
11/14/2000US6147359 Method of making silicon quantum wires
11/14/2000US6147356 Arrangement for the detection of disk-shaped objects in a cassette
11/14/2000US6147355 Pattern forming method
11/14/2000US6147334 Laminated paddle heater and brazing process
11/14/2000US6147329 Resist processing system and resist processing method
11/14/2000US6147311 Multi layer circuit board using anisotropic electroconductive adhesive layer and method for producing same
11/14/2000US6147141 Die attach adhesive compositions
11/14/2000US6147042 Detergent for processes for producing semiconductor devices or producing liquid crystal devices
11/14/2000US6147014 Reacting an ammonia compound with a silane compound, wherein at least one of said compounds contains deuterium, so as to form a silicon nitride spacer containing deuterium.
11/14/2000US6147013 Method of LPCVD silicon nitride deposition
11/14/2000US6147012 Process for forming low k silicon oxide dielectric material while suppressing pressure spiking and inhibiting increase in dielectric constant
11/14/2000US6147011 In the presence of activated fluorine, a dielectric layer is chemical vapor deposited over the substrate
11/14/2000US6147010 Solvent having a low vapor pressure, wherein the vapor pressure of the solvent is equal to or is lower than the vapor pressure of diacetone alcohol; wherein said solvent comprises diacetone alcohol
11/14/2000US6147009 Hydrogenated oxidized silicon carbon material
11/14/2000US6147008 Creation of multiple gate oxide with high thickness ratio in flash memory process
11/14/2000US6147007 Method for forming a contact hole on a semiconductor wafer
11/14/2000US6147006 Cleaning gas
11/14/2000US6147005 Method of forming dual damascene structures
11/14/2000US6147004 Jet vapor reduction of the thickness of process layers
11/14/2000US6147003 Method of manufacturing semiconductor device
11/14/2000US6147002 Aqueous composition comprising a fluoride containing compound; a dicarboxylic acid and/or salt thereof; and a hydroxycarboxylic acid and/or salt thereof.
11/14/2000US6147001 Method of manufacturing semiconductor integrated circuit device
11/14/2000US6147000 Method for forming low dielectric passivation of copper interconnects
11/14/2000US6146999 Method for forming metal line of semiconductor device
11/14/2000US6146998 Forming a first titanium nitride layer on the titanium layer without introducing oxygen; forming a titanium oxynitride layer on the first titanium nitride layer; forming a second titanium nitride layer on the titanium oxynitride layer
11/14/2000US6146997 Method for forming self-aligned contact hole
11/14/2000US6146996 Semiconductor device with conductive via and method of making same
11/14/2000US6146995 Can avoid the formation of recesses on plug surface.
11/14/2000US6146994 Method for forming self-aligned selective silicide layer using chemical mechanical polishing in merged DRAM logic
11/14/2000US6146993 Method for forming in-situ implanted semiconductor barrier layers
11/14/2000US6146992 Vertically integrated semiconductor component and method of producing the same
11/14/2000US6146991 Barrier metal composite layer featuring a thin plasma vapor deposited titanium nitride capping layer
11/14/2000US6146990 Method of forming contact plug
11/14/2000US6146989 Method of fabricating semiconductor device with cavity interposed between wirings
11/14/2000US6146988 Method of making a semiconductor device comprising copper interconnects with reduced in-line copper diffusion
11/14/2000US6146987 Method for forming a contact plug over an underlying metal line using an etching stop layer
11/14/2000US6146986 Lithographic method for creating damascene metallization layers
11/14/2000US6146984 Method and structure for uniform height solder bumps on a semiconductor wafer
11/14/2000US6146983 Having a stacked silicide metal
11/14/2000US6146982 Method for producing a low-impedance contact between a metallizing layer and a semiconductor material
11/14/2000US6146981 Method of manufacturing buried contact in SRAM
11/14/2000US6146980 Method for manufacturing silicon substrate having gettering capability
11/14/2000US6146979 Pressurized microbubble thin film separation process using a reusable substrate
11/14/2000US6146978 Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance
11/14/2000US6146977 Method of manufacturing a radiation-resistant semiconductor integrated circuit
11/14/2000US6146976 Method for producing bridged doped zones
11/14/2000US6146975 Shallow trench isolation
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