Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2000
12/19/2000US6163050 Semiconductor device having insulation film whose breakdown voltage is improved and its manufacturing method
12/19/2000US6163049 Method of forming a composite interpoly gate dielectric
12/19/2000US6163047 Method of fabricating a self aligned contact for a capacitor over bitline, (COB), memory cell
12/19/2000US6163046 Semiconductor device and method of fabricating semiconductor device
12/19/2000US6163045 Reduced parasitic leakage in semiconductor devices
12/19/2000US6163042 Semiconductor integrated circuit
12/19/2000US6163041 Field effect transistor and method of manufacturing the same
12/19/2000US6163040 Thyristor manufacturing method and thyristor
12/19/2000US6163033 Method and apparatus for controlling a workpiece in a vacuum chamber
12/19/2000US6163015 Substrate support element
12/19/2000US6163007 Microwave plasma generating apparatus with improved heat protection of sealing O-rings
12/19/2000US6163006 Permanent magnet ECR plasma source with magnetic field optimization
12/19/2000US6162997 Circuit board with primary and secondary through holes
12/19/2000US6162988 Photovoltaic element
12/19/2000US6162838 Thermal removing organic material from mixture of organic material and dielectric
12/19/2000US6162745 Film forming method
12/19/2000US6162744 Method of forming capacitors having high-K oxygen containing capacitor dielectric layers, method of processing high-K oxygen containing dielectric layers, method of forming a DRAM cell having having high-K oxygen containing capacitor dielectric layers
12/19/2000US6162743 Low dielectric constant film and method thereof
12/19/2000US6162741 Semiconductor device and manufacturing method therefor
12/19/2000US6162740 Semiconductor device and method of forming semiconductor device
12/19/2000US6162739 Process for wet etching of semiconductor wafers
12/19/2000US6162738 Cleaning stack of tantalum pentaoxide having etch residue with aqueous solution containing hydrochloric acid and hydrogen peroxide
12/19/2000US6162737 Films doped with carbon for use in integrated circuit technology
12/19/2000US6162736 Process for fabricating a semiconductor integrated circuit utilizing an exposure method
12/19/2000US6162735 In-situ method for preparing and highlighting of defects for failure analysis
12/19/2000US6162734 Semiconductor processing using vapor mixtures
12/19/2000US6162733 Method for removing contaminants from integrated circuits
12/19/2000US6162732 Method for reducing capacitance depletion during hemispherical grain polysilicon synthesis for DRAM
12/19/2000US6162731 Method of defining a conductive layer
12/19/2000US6162730 Method for fabricating semiconductor wafers
12/19/2000US6162729 Filling in wiring connection hole; low temperature sputtering
12/19/2000US6162728 Method to optimize copper chemical-mechanical polishing in a copper damascene interconnect process for integrated circuit applications
12/19/2000US6162727 Surface treatment with acetic acid and ammonium fluoride solution
12/19/2000US6162726 Gas shielding during plating
12/19/2000US6162725 Process of patterning conductive layer into electrode through lift-off using photo-resist mask imperfectly covered with the conductive layer
12/19/2000US6162724 Method for forming metalization for inter-layer connections
12/19/2000US6162723 Method of fabricating a semiconductor integrated circuit device having an interlevel dielectric layer with voids between narrowly-spaced wiring lines
12/19/2000US6162722 Unlanded via process
12/19/2000US6162721 Semiconductor processing methods
12/19/2000US6162720 Semiconductor device and method of manufacturing the same
12/19/2000US6162718 High speed bump plating/forming
12/19/2000US6162717 Method of manufacturing MOS gate utilizing a nitridation reaction
12/19/2000US6162716 Amorphous silicon gate with mismatched grain-boundary microstructure
12/19/2000US6162715 Method of forming gate electrode connection structure by in situ chemical vapor deposition of tungsten and tungsten nitride
12/19/2000US6162714 Method of forming thin polygates for sub quarter micron CMOS process
12/19/2000US6162713 Method for fabricating semiconductor structures having metal silicides
12/19/2000US6162712 Platinum source compositions for chemical vapor deposition of platinum
12/19/2000US6162711 In-situ boron doped polysilicon with dual layer and dual grain structure for use in integrated circuits manufacturing
12/19/2000US6162710 Method for making MIS transistor
12/19/2000US6162709 Use of an asymmetric waveform to control ion bombardment during substrate processing
12/19/2000US6162706 Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic
12/19/2000US6162705 Controlled cleavage process and resulting device using beta annealing
12/19/2000US6162704 Method of making semiconductor device
12/19/2000US6162703 Packaging die preparation
12/19/2000US6162702 Self-supported ultra thin silicon wafer process
12/19/2000US6162701 Semiconductor device and method for making same
12/19/2000US6162700 Method of forming a trench isolation structure in a semiconductor substrate
12/19/2000US6162699 Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery
12/19/2000US6162698 Method of manufacturing a capacitor in a semiconductor device
12/19/2000US6162697 High Q inductor realization for use in MMIC circuits
12/19/2000US6162696 Method of fabricating a feature in an integrated circuit using a two mask process with a single edge definition layer
12/19/2000US6162695 Field ring to improve the breakdown voltage for a high voltage bipolar device
12/19/2000US6162694 Method of forming a metal gate electrode using replaced polysilicon structure
12/19/2000US6162693 Channel implant through gate polysilicon
12/19/2000US6162692 Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor
12/19/2000US6162691 Method for forming a MOSFET with raised source and drain, saliciding, and removing upper portion of gate spacers if bridging occurs
12/19/2000US6162690 Methods of forming field effect transistors having self-aligned intermediate source and drain contacts
12/19/2000US6162689 Multi-depth junction formation tailored to silicide formation
12/19/2000US6162688 Method of fabricating a transistor with a dielectric underlayer and device incorporating same
12/19/2000US6162687 Method of manufacturing semiconductor device having oxide-nitride gate insulating layer
12/19/2000US6162685 Method of fabricating flash memory
12/19/2000US6162684 Ammonia annealed and wet oxidized LPCVD oxide to replace ono films for high integrated flash memory devices
12/19/2000US6162683 System and method for forming an inter-layer dielectric in floating gate memory devices
12/19/2000US6162682 Structure and process for a gouge-free stacked non-volatile memory cell with select gate
12/19/2000US6162681 DRAM cell with a fork-shaped capacitor
12/19/2000US6162680 Method for forming a DRAM capacitor
12/19/2000US6162679 Method of manufacturing DRAM capacitor
12/19/2000US6162678 Simple small feature size bit line formation in DRAM with RTO oxidation
12/19/2000US6162677 Semiconductor device fabricating method
12/19/2000US6162676 Method of making a semiconductor device with an etching stopper
12/19/2000US6162675 Method of preventing misalignment of selective silicide layer in the manufacture of a DRAM device and the DRAM device formed thereby
12/19/2000US6162674 Method of manufacturing semiconductor device
12/19/2000US6162673 Method of manufacturing SRAM cell
12/19/2000US6162672 Method for forming integrated circuit memory devices with high and low dopant concentration regions of different diffusivities
12/19/2000US6162671 Method of forming capacitors having high dielectric constant material
12/19/2000US6162670 Method of fabricating a data-storage capacitor for a dynamic random-access memory device
12/19/2000US6162669 Method of manufacturing a semiconductor device having an LDD structure with a recess in the source/drain region formed during removal of a damaged layer
12/19/2000US6162668 Method of manufacturing a semiconductor device having a lightly doped contact impurity region surrounding a highly doped contact impurity region
12/19/2000US6162667 Method for fabricating thin film transistors
12/19/2000US6162666 Exposure to ozone and ultraviolet light
12/19/2000US6162665 High voltage transistors and thyristors
12/19/2000US6162662 Die paddle clamping method for wire bond enhancement
12/19/2000US6162661 Spacer plate solder ball placement fixture and methods therefor
12/19/2000US6162660 Method for joining a semiconductor chip to a chip carrier substrate and resulting chip package
12/19/2000US6162652 Process for sort testing C4 bumped wafers
12/19/2000US6162651 Method and system for accurately marking the backside of the die for fault location isolation
12/19/2000US6162649 Forming platinum layer containing oxygen for upper electrode of capacitor
12/19/2000US6162603 Hybridization of polynucleotides conjugated with chromophores and fluorophores to generate donor-to-donor energy transfer system
12/19/2000US6162591 Photolithography process with gas-phase pretreatment
12/19/2000US6162587 Forming dielectric layer on antireflective coating; patterning
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