Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2000
11/28/2000US6153534 Method for fabricating a dual material gate of a short channel field effect transistor
11/28/2000US6153533 Method of using a compliant process cassette
11/28/2000US6153532 Methods and apparatuses for removing material from discrete areas on a semiconductor wafer
11/28/2000US6153531 Method for preventing electrochemical erosion of interconnect structures
11/28/2000US6153530 Post-etch treatment of plasma-etched feature surfaces to prevent corrosion
11/28/2000US6153528 Method of fabricating a dual damascene structure
11/28/2000US6153527 Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material
11/28/2000US6153526 Method to remove residue in wolfram CMP
11/28/2000US6153525 Curing; on semiconductor substrate
11/28/2000US6153524 Cluster tool method using plasma immersion ion implantation
11/28/2000US6153523 Method of forming high density capping layers for copper interconnects with improved adhesion
11/28/2000US6153522 Semiconductor device manufacturing method
11/28/2000US6153521 Metallized interconnection structure and method of making the same
11/28/2000US6153520 Vapor deposition
11/28/2000US6153519 Method of forming a barrier layer
11/28/2000US6153518 Method of making chip size package substrate
11/28/2000US6153517 Low resistance poly landing pad
11/28/2000US6153516 Method of fabricating a modified polysilicon plug structure
11/28/2000US6153515 Method of forming multilayered film
11/28/2000US6153514 Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer
11/28/2000US6153513 Method of fabricating self-aligned capacitor
11/28/2000US6153512 Process to improve adhesion of HSQ to underlying materials
11/28/2000US6153511 Semiconductor device having a multilayered interconnection structure
11/28/2000US6153510 Semiconductor device and method for manufacturing the same, and semiconductor memory device and method for manufacturing the same
11/28/2000US6153509 Forming metal wirings on dielectric film
11/28/2000US6153507 Method of fabricating semiconductor device providing effective resistance against metal layer oxidation and diffusion
11/28/2000US6153505 Plastic solder array using injection molded solder
11/28/2000US6153504 Multilayer semiconductor; antirefelective overcoating
11/28/2000US6153503 Continuous process for producing solder bumps on electrodes of semiconductor chips
11/28/2000US6153502 Method of fabricating semiconductor device having analog properties
11/28/2000US6153501 Method of reducing overetch during the formation of a semiconductor device
11/28/2000US6153500 Atomic wire and atomic wire switch
11/28/2000US6153499 Method of manufacturing semiconductor device
11/28/2000US6153498 Method of fabricating a buried contact
11/28/2000US6153497 Method for determining a cause for defects in a film deposited on a wafer
11/28/2000US6153496 Process for the production of polycrystalline silicon mouldings substantially free of edge regions and the use of these mouldings
11/28/2000US6153495 Advanced methods for making semiconductor devices by low temperature direct bonding
11/28/2000US6153494 Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash
11/28/2000US6153493 Method of manufacturing semiconductor device
11/28/2000US6153491 Overhanging separator for self-defining discontinuous film
11/28/2000US6153490 Method for forming integrated circuit capacitor and memory
11/28/2000US6153489 Forming trench in silicone substrate; filling with porous silicon; forming dielectric; forming metal pattern
11/28/2000US6153488 Method for producing semiconductor device, and semiconductor device produced by same
11/28/2000US6153487 Approach for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects
11/28/2000US6153486 Method for establishing shallow junction in semiconductor device to minimize junction capacitance
11/28/2000US6153485 Forming transistors
11/28/2000US6153484 Controlling the etching rate of cobalt disilicide layers by adjusting the ph of a hydrofluoric acid based solution to obtain the desired etch rate
11/28/2000US6153483 Overcoating with silicon nitride; anisotropic and isotropic etching
11/28/2000US6153482 Method for fabricating LOCOS isolation having a planar surface which includes having the polish stop layer at a lower level than the LOCOS formation
11/28/2000US6153481 Method for forming an isolation insulating film for internal elements of a semiconductor device
11/28/2000US6153480 Forming trench in substrate; exposure to nitrogen; forming oxide with nitride interface
11/28/2000US6153479 Method of fabricating shallow trench isolation structures
11/28/2000US6153478 STI process for eliminating kink effect
11/28/2000US6153477 Ultra short transistor channel length formed using a gate dielectric having a relatively high dielectric constant
11/28/2000US6153476 Semiconductor device and method for manufacturing the same
11/28/2000US6153475 Method for the manufacturing a memory cell configuration
11/28/2000US6153474 Method of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrate
11/28/2000US6153473 Method of symmetrically implanted punch-through stopper for a rugged DMOS power device
11/28/2000US6153472 Method for fabricating a flash memory
11/28/2000US6153471 Method of fabricating flash memory
11/28/2000US6153470 Floating gate engineering to improve tunnel oxide reliability for flash memory devices
11/28/2000US6153469 Method of fabricating cell of flash memory device
11/28/2000US6153467 Method of fabricating high density buried bit line flash EEPROM memory cell with a shallow trench floating gate
11/28/2000US6153466 Method for increasing capacitance
11/28/2000US6153465 Method of fabricating a capacitor of dynamic random access memory
11/28/2000US6153464 Method of fabricating a semiconductor memory device having a branching capacitor
11/28/2000US6153463 Triple plate capacitor and method for manufacturing
11/28/2000US6153462 Manufacturing process and structure of capacitor
11/28/2000US6153461 Manufacturing method of a dielectric layer for DRAM capacitors
11/28/2000US6153460 Method of fabricating semiconductor memory device
11/28/2000US6153459 Method of fabricating dual gate structure of embedded DRAM
11/28/2000US6153458 Method of forming a portion of a memory cell
11/28/2000US6153457 Method of fabricating self-align-contact
11/28/2000US6153456 Method of selectively applying dopants to an integrated circuit semiconductor device without using a mask
11/28/2000US6153455 Forming barrier; isotropic etching
11/28/2000US6153454 Convex device with selectively doped channel
11/28/2000US6153453 JFET transistor manufacturing method
11/28/2000US6153452 Method of manufacturing semiconductor devices having improved polycide integrity through introduction of a silicon layer within the polycide structure
11/28/2000US6153451 Transistor with increased operating voltage and method of fabrication
11/28/2000US6153450 Method of utilizing fuses to select alternative modules in a semiconductor device
11/28/2000US6153449 For semiconductors
11/28/2000US6153448 Overcoating source, drain and gate zones; positioning silicon dioxide spacer between drains and gate; etching
11/28/2000US6153447 LSI package and manufacturing method thereof
11/28/2000US6153445 Doping amophous silicon film; crystallization
11/28/2000US6153444 Method of measuring free carrier concentration and/or thickness of a semiconductor and process of manufacturing semiconductor device and semiconductor wafer using such method
11/28/2000US6153443 Method of fabricating a magnetic random access memory
11/28/2000US6153361 Method of removing photoresist at the edge of wafers
11/28/2000US6153360 Using deionized water, acetone and pyrrolidone
11/28/2000US6153357 Exposure, forming pattern, phase shifting cycles
11/28/2000US6153354 Electron beam negative working resist composition
11/28/2000US6153349 Comprising polyvinylphenol derivative resin
11/28/2000US6153340 Charged-particle-beam microlithography methods and reticles for same exhibiting reduced space-charge and proximity effects
11/28/2000US6153320 Laminated ferromagnetic layers containing antiferromagnetically coupled ferromagnetic films joining together with improved antiferromagnetically coupling films which are made of an alloy of ruthenium, osmium and rhenium
11/28/2000US6153317 Perovskite phase thin films and method of making
11/28/2000US6153290 Multi-layer ceramic substrate and method for producing the same
11/28/2000US6153269 Monomer gas is exposed to a source of heat having a temperature sufficient to pyrolyze the monomer gas and produce a source of reactive cf2 species in the vicinity of the structure surface
11/28/2000US6153261 Self-decomposition of vapor deposited title silicon source to form a silicon nitride or oxynitride dielectric film on substrate with good step coverage and gap filling
11/28/2000US6153260 Method for heating exhaust gas in a substrate reactor
11/28/2000US6153165 A complex in which a polycrystalline plate consisting of silicon and carbon atoms is stacked on the surface of a single crystal silicon carbide base and is subjected to heat treatment, which transforms polycrystals to single crystal
11/28/2000US6153141 Inserting molding material into container; applying gradient heat to molding material in container to make molding material more malleable; forcing molding material from container into mold while allowing air to escape
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