Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2000
12/26/2000US6166427 Integration of low-K SiOF as inter-layer dielectric for AL-gapfill application
12/26/2000US6166426 Lateral bipolar transistors and systems using such
12/26/2000US6166425 Semiconductor device having a resistance element with a reduced area
12/26/2000US6166424 Capacitance structure for preventing degradation of the insulating film
12/26/2000US6166423 Integrated circuit having a via and a capacitor
12/26/2000US6166420 Method and structure of high and low K buried oxide for SoI technology
12/26/2000US6166419 Semiconductor memory device
12/26/2000US6166417 Complementary metal gates and a process for implementation
12/26/2000US6166416 CMOS analog semiconductor apparatus and fabrication method thereof
12/26/2000US6166415 Semiconductor device with improved noise resistivity
12/26/2000US6166414 Electronic circuit
12/26/2000US6166413 Semiconductor device having field effect transistors different in thickness of gate electrodes and process of fabrication thereof
12/26/2000US6166412 SOI device with double gate and method for fabricating the same
12/26/2000US6166411 Heat removal from SOI devices by using metal substrates
12/26/2000US6166410 MONOS flash memory for multi-level logic and method thereof
12/26/2000US6166409 Flash EPROM memory cell having increased capacitive coupling
12/26/2000US6166408 Hexagonally symmetric integrated circuit cell
12/26/2000US6166406 Precharge circuit and semiconductor storage device
12/26/2000US6166404 Semiconductor device in which at least two field effect transistors having different threshold voltages are formed on a common base
12/26/2000US6166403 Integrated circuit having embedded memory with electromagnetic shield
12/26/2000US6166402 Pressure-contact type semiconductor element and power converter thereof
12/26/2000US6166400 Thin film transistor of liquid crystal display with amorphous silicon active layer and amorphous diamond ohmic contact layers
12/26/2000US6166399 Active matrix device including thin film transistors
12/26/2000US6166398 Thin film transistors
12/26/2000US6166397 Display device with inverted type transistors in the peripheral and pixel portions
12/26/2000US6166396 Semiconductor devices
12/26/2000US6166395 Amorphous silicon interconnect with multiple silicon layers
12/26/2000US6166386 Micro-processing method using a probe
12/26/2000US6166333 Bumps with plural under-bump dielectric layers
12/26/2000US6166328 Package stack via bottom leaded plastic (BLP) packaging
12/26/2000US6165956 Solution for dissolving copper oxides comprising hydrogen fluoride, citric acid, ammonium hydroxide in deionized water
12/26/2000US6165918 Method for forming gate oxides of different thicknesses
12/26/2000US6165917 Plasma-enhanced chemical vapor depositiin of a layer of ammonia-free silicon nitride between the copper, aluminum, or other refractory metal gate and the gate insulator of a thin film transistor (tft) for use in a liquid crystal display
12/26/2000US6165916 Film-forming method and film-forming apparatus
12/26/2000US6165915 Forming halogen doped glass dielectric layer with enhanced stability
12/26/2000US6165914 Method for fabricating semiconductor devices with thick high quality oxides
12/26/2000US6165913 Manufacturing method for spacer
12/26/2000US6165912 Electroless metal deposition of electronic components in an enclosable vessel
12/26/2000US6165911 Method of patterning a metal layer
12/26/2000US6165910 Self-aligned contacts for semiconductor device
12/26/2000US6165909 Method for fabricating capacitor
12/26/2000US6165908 Single-layer-electrode type charge coupled device having double conductive layers for charge transfer electrodes
12/26/2000US6165907 Plasma etching method and plasma etching apparatus
12/26/2000US6165906 Semiconductor topography employing a shallow trench isolation structure with an improved trench edge
12/26/2000US6165905 Methods for making reliable via structures having hydrophobic inner wall surfaces
12/26/2000US6165904 Polishing pad for use in the chemical/mechanical polishing of a semiconductor substrate and method of polishing the substrate using the pad
12/26/2000US6165903 Method of forming ultra-shallow junctions in a semiconductor wafer with deposited silicon layer to reduce silicon consumption during salicidation
12/26/2000US6165902 Low resistance metal contact technology
12/26/2000US6165901 Method of fabricating self-aligned contact
12/26/2000US6165900 Method for manufacturing semiconductor device
12/26/2000US6165899 Method for manufacturing semiconductor devices having dual damascene structure
12/26/2000US6165898 Dual damascene patterned conductor layer formation method without etch stop layer
12/26/2000US6165897 Void forming method for fabricating low dielectric constant dielectric layer
12/26/2000US6165896 Self-aligned formation and method for semiconductors
12/26/2000US6165895 Fabrication method of an interconnect
12/26/2000US6165894 Method of reliably capping copper interconnects
12/26/2000US6165893 Insulating layers and a forming method thereof
12/26/2000US6165892 Method of planarizing thin film layers deposited over a common circuit base
12/26/2000US6165891 Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer
12/26/2000US6165890 Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections
12/26/2000US6165889 Process for forming trenches and contacts during the formation of a semiconductor memory device
12/26/2000US6165888 Two step wire bond process
12/26/2000US6165887 Method of improving interconnect of semiconductor devices by using a flattened ball bond
12/26/2000US6165886 Advanced IC bonding pad design for preventing stress induced passivation cracking and pad delimitation through stress bumper pattern and dielectric pin-on effect
12/26/2000US6165885 Method of making components with solder balls
12/26/2000US6165884 Method of forming gate electrode in semiconductor device
12/26/2000US6165883 Method for forming multilayer sidewalls on a polymetal stack gate electrode
12/26/2000US6165882 Polysilicon gate having a metal plug, for reduced gate resistance, within a trench extending into the polysilicon layer of the gate
12/26/2000US6165881 Method of forming salicide poly gate with thin gate oxide and ultra narrow gate width
12/26/2000US6165880 Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
12/26/2000US6165879 Method for improving manufacturing process of self-aligned contact
12/26/2000US6165878 Method of manufacturing semiconductor device
12/26/2000US6165877 Method for establishing shallow junction in semiconductor device to minimize junction capacitance
12/26/2000US6165876 Method of doping crystalline silicon film
12/26/2000US6165874 Method for growth of crystal surfaces and growth of heteroepitaxial single crystal films thereon
12/26/2000US6165873 Process for manufacturing a semiconductor integrated circuit device
12/26/2000US6165872 Semiconductor device and its manufacturing method
12/26/2000US6165871 Method of making low-leakage architecture for sub-0.18 μm salicided CMOS device
12/26/2000US6165870 Element isolation method for semiconductor devices including etching implanted region under said spacer to form a stepped trench structure
12/26/2000US6165869 Method to avoid dishing in forming trenches for shallow trench isolation
12/26/2000US6165868 Monolithic device isolation by buried conducting walls
12/26/2000US6165867 Method to reduce aspect ratio of DRAM peripheral contact
12/26/2000US6165865 Method of fabricating dual cylindrical capacitor
12/26/2000US6165864 Tapered electrode for stacked capacitors
12/26/2000US6165863 Aluminum-filled self-aligned trench for stacked capacitor structure and methods
12/26/2000US6165862 Method of producing a thin film resistor
12/26/2000US6165861 Integrated circuit polysilicon resistor having a silicide extension to achieve 100% metal shielding from hydrogen intrusion
12/26/2000US6165860 Semiconductor device with reduced photolithography steps
12/26/2000US6165859 Method for making InP heterostructure devices
12/26/2000US6165858 Enhanced silicidation formation for high speed MOS device by junction grading with dual implant dopant species
12/26/2000US6165857 Method for forming a transistor with selective epitaxial growth film
12/26/2000US6165856 Using an organic layer as an ion implantation mask when forming shallow source/drain region
12/26/2000US6165855 Antireflective coating used in the fabrication of microcircuit structures in 0.18 micron and smaller technologies
12/26/2000US6165854 Method to form shallow trench isolation with an oxynitride buffer layer
12/26/2000US6165853 Trench isolation method
12/26/2000US6165852 Method of fabricating integration of high-voltage devices and low-voltage devices
12/26/2000US6165851 Semiconductor nonvolatile storage and method of fabricating the same
12/26/2000US6165850 Method of manufacturing mask read-only-memory
12/26/2000US6165849 Method of manufacturing mosfet with differential gate oxide thickness on the same IC chip
12/26/2000US6165848 Method for the production of a MOS-controlled power semiconductor component
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