| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 01/30/2001 | US6180529 Method of making an image sensor or LCD including switching pin diodes |
| 01/30/2001 | US6180528 Method for forming a minute resist pattern and method for forming a gate electrode |
| 01/30/2001 | US6180527 Method and apparatus for thinning article, and article |
| 01/30/2001 | US6180526 Method for improving conformity of a conductive layer in a semiconductor device |
| 01/30/2001 | US6180525 Method of minimizing repetitive chemical-mechanical polishing scratch marks and of processing a semiconductor wafer outer surface |
| 01/30/2001 | US6180524 Rinsing in oxygen-free ammonia solution; drainage; electroless metal deposition; electroplating |
| 01/30/2001 | US6180523 Forming contact hole in insulating layer exposing substrate; forming an adhesion layer on sidewalls of insulating layer and exposed substrate; electrolessly depositing barrier layer; activating; electrolessly plating; patterning |
| 01/30/2001 | US6180522 Method of forming a contact in a semiconductor device |
| 01/30/2001 | US6180521 Process for manufacturing a contact barrier |
| 01/30/2001 | US6180520 Multiple layer interconnects with low stray lateral capacitance |
| 01/30/2001 | US6180519 Method of forming a layered wiring structure including titanium silicide |
| 01/30/2001 | US6180518 Method for forming vias in a low dielectric constant material |
| 01/30/2001 | US6180517 Method of forming submicron contacts and vias in an integrated circuit |
| 01/30/2001 | US6180516 Forming dielectric layer having conductive layer on dielectric layer, photoresist layer having opening; etching dielectric layer to form trench; forming titanium layer and photoresist layer; etching titanium layer; removing; planarizing |
| 01/30/2001 | US6180515 Forming gate oxide layer on semiconductor substrate; forming polysilicon layer; forming silicon nitride layer; patterning silicon nitride layer, polysilicon layer and gate oxide layer to form gate structure having cap layer; etching |
| 01/30/2001 | US6180514 Method for forming interconnect using dual damascene |
| 01/30/2001 | US6180513 Apparatus and method for manufacturing a semiconductor device having a multi-wiring layer structure |
| 01/30/2001 | US6180512 Single-mask dual damascene processes by using phase-shifting mask |
| 01/30/2001 | US6180511 Forming first insulating layer on semiconductor substrate having device such as transistors; forming metal wirings in which titanium/titanium nitride(tin)layer, al layer and tin layer are stacked; forming spacer of tin layer; polishing |
| 01/30/2001 | US6180510 Method of manufacturing a substantially flat surface of a semiconductor device through a polishing operation |
| 01/30/2001 | US6180509 Method for forming planarized multilevel metallization in an integrated circuit |
| 01/30/2001 | US6180508 Methods of fabricating buried digit lines and semiconductor devices including same |
| 01/30/2001 | US6180507 Method of forming interconnections |
| 01/30/2001 | US6180506 Upper redundant layer for damascene metallization |
| 01/30/2001 | US6180505 Forming bulk copper-containing film indirectly on substrate; roughening; laminating impurity film on surface; patterning; forming transition film; covering with gold film; heating structure to produce chemical mixture along interface |
| 01/30/2001 | US6180502 Self-aligned process for making asymmetric MOSFET using spacer gate technique |
| 01/30/2001 | US6180501 Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process |
| 01/30/2001 | US6180500 Method of creating ultra-small nibble structures during MOSFET fabrication |
| 01/30/2001 | US6180499 Method for forming polysilicon-germanium gate in CMOS transistor and device made thereby |
| 01/30/2001 | US6180498 Alignment targets having enhanced contrast |
| 01/30/2001 | US6180497 Method for producing semiconductor base members |
| 01/30/2001 | US6180496 Cleaning wafers, rinsing and drying; placing wafers into plasma chamber equipped with bonding apparatus; exposing wafers to plasma which reduces surface; without breaking vacuum, placing wafer surfaces together and into contact |
| 01/30/2001 | US6180495 Silicon carbide transistor and method therefor |
| 01/30/2001 | US6180494 Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines |
| 01/30/2001 | US6180493 Method for forming shallow trench isolation region |
| 01/30/2001 | US6180492 Method of forming a liner for shallow trench isolation |
| 01/30/2001 | US6180491 Isolation structure and method |
| 01/30/2001 | US6180490 Providing silicon substrate having trench formed; forming special trench liner layer of silicon dioxide film by chemical vapor deposition; oxidizing substrate; depositing silicon dioxide layer; annealing; planarizing excess fill material |
| 01/30/2001 | US6180489 Formation of finely controlled shallow trench isolation for ULSI process |
| 01/30/2001 | US6180488 Method of forming separating region of semiconductor device |
| 01/30/2001 | US6180487 Selective thinning of barrier oxide through masked SIMOX implant |
| 01/30/2001 | US6180486 Process of fabricating planar and densely patterned silicon-on-insulator structure |
| 01/30/2001 | US6180485 Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits |
| 01/30/2001 | US6180484 Forming tungsten layer having surface on semiconductor substrate, whereby plurality of spires are formed on surface of tungsten layer; bombarding surface of tungsten layer with chemical plasma ions thereby rounding spires |
| 01/30/2001 | US6180483 Structure and fabrication method for multiple crown capacitor |
| 01/30/2001 | US6180482 Method for manufacturing high dielectric capacitor |
| 01/30/2001 | US6180481 Barrier layer fabrication methods |
| 01/30/2001 | US6180480 Germanium or silicon-germanium deep trench fill by melt-flow process |
| 01/30/2001 | US6180479 Method of etching to form high tolerance polysilicon resistors |
| 01/30/2001 | US6180478 Fabrication process for a single polysilicon layer, bipolar junction transistor featuring reduced junction capacitance |
| 01/30/2001 | US6180477 Method of fabricating field effect transistor with silicide sidewall spacers |
| 01/30/2001 | US6180476 Dual amorphization implant process for ultra-shallow drain and source extensions |
| 01/30/2001 | US6180475 Transistor formation with local interconnect overetch immunity |
| 01/30/2001 | US6180474 Method for fabricating semiconductor device |
| 01/30/2001 | US6180473 Method for manufacturing semiconductor device |
| 01/30/2001 | US6180472 Method for fabricating semiconductor device |
| 01/30/2001 | US6180471 Method of fabricating high voltage semiconductor device |
| 01/30/2001 | US6180470 FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements |
| 01/30/2001 | US6180469 Low resistance salicide technology with reduced silicon consumption |
| 01/30/2001 | US6180468 Very low thermal budget channel implant process for semiconductors |
| 01/30/2001 | US6180467 Method of fabricating shallow trench isolation |
| 01/30/2001 | US6180466 Isotropic assisted dual trench etch |
| 01/30/2001 | US6180465 Method of making high performance MOSFET with channel scaling mask feature |
| 01/30/2001 | US6180464 Metal oxide semiconductor device with localized laterally doped channel |
| 01/30/2001 | US6180463 Method for fabricating a multi-level mask ROM |
| 01/30/2001 | US6180461 Double sidewall short channel split gate flash memory |
| 01/30/2001 | US6180460 Process for manufacturing of a non volatile memory with reduced resistance of the common source lines |
| 01/30/2001 | US6180459 Method for fabricating a flash memory with shallow trench isolation |
| 01/30/2001 | US6180458 Method of producing a memory cell configuration |
| 01/30/2001 | US6180457 Method of manufacturing non-volatile memory device |
| 01/30/2001 | US6180456 Triple polysilicon embedded NVRAM cell and method thereof |
| 01/30/2001 | US6180455 Semiconductor device and method of manufacturing the same |
| 01/30/2001 | US6180454 Method for forming flash memory devices |
| 01/30/2001 | US6180453 Method to fabricate a DRAM cell with an area equal to five times the minimum used feature, squared |
| 01/30/2001 | US6180452 Shared length cell for improved capacitance |
| 01/30/2001 | US6180451 Method of forming capacitor with a HSG layer |
| 01/30/2001 | US6180450 Semiconductor processing methods of forming stacked capacitors |
| 01/30/2001 | US6180449 Depletion compensated polysilicon electrodes |
| 01/30/2001 | US6180448 Semiconductor memory device having a capacitor over bitline structure and method for manufacturing the same |
| 01/30/2001 | US6180447 Methods for fabricating integrated circuit capacitors including barrier layers having grain boundary filling material |
| 01/30/2001 | US6180446 Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K DRAMS using disposable-oxide processing |
| 01/30/2001 | US6180444 Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same |
| 01/30/2001 | US6180443 Semiconductor device and method of fabricating the same |
| 01/30/2001 | US6180442 Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method |
| 01/30/2001 | US6180441 Bar field effect transistor |
| 01/30/2001 | US6180440 Method of fabricating a recessed-gate FET without producing voids in the gate metal |
| 01/30/2001 | US6180439 Method for fabricating a semiconductor device |
| 01/30/2001 | US6180438 Thin film transistors and electronic devices comprising such |
| 01/30/2001 | US6180435 Semiconductor device with economical compact package and process for fabricating semiconductor device |
| 01/30/2001 | US6180430 Methods to reduce light leakage in LCD-on-silicon devices |
| 01/30/2001 | US6180429 Depositing on iii-v semiconductor substrate semiconductor layers; forming lift-off mask layer comprising etch mask and spacer layers; lithographically masking; etching; selectively forming semiconductor blocking layer; removing spacer layer |
| 01/30/2001 | US6180426 High performance sub-system design and assembly |
| 01/30/2001 | US6180424 Method for improving wafer sleuth capability by adding wafer rotation tracking |
| 01/30/2001 | US6180423 Method for wafer polishing and method for polishing pad dressing |
| 01/30/2001 | US6180422 Endpoint detection by chemical reaction |
| 01/30/2001 | US6180420 Low temperature CVD processes for preparing ferroelectric films using Bi carboxylates |
| 01/30/2001 | US6180322 Developing thin film, made from radiation sensitive composition comprising alkali-soluble resin and radiation sensitive compound and having latent image pattern, with alkaline developing solution to form thin film pattern wherein |
| 01/30/2001 | US6180321 Preparing semiconductor substrate with thin film layer, intermediate layer and photoresist layer; exposing partial depth of photoresist layer to light beam; removing portion of photoresist layer exposed to light; patterning |
| 01/30/2001 | US6180320 Resist pattern is formed on semiconductor substrate through use of acid catalyst chemically-amplified photoresist and forming organic film which includes acid or which produces acid on exposure to light; heat treating film to diffuse acid |
| 01/30/2001 | US6180293 Mask pattern preparing method and photomask |