| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
|---|
| 01/09/2001 | US6172380 Semiconductor material |
| 01/09/2001 | US6172376 Method and system for measuring particles in a liquid sample |
| 01/09/2001 | US6172370 Lateral PN arrayed digital x-ray image sensor |
| 01/09/2001 | US6172365 Electron beam inspection method and apparatus and semiconductor manufacturing method and its manufacturing line utilizing the same |
| 01/09/2001 | US6172364 Charged particle beam irradiation apparatus |
| 01/09/2001 | US6172337 System and method for thermal processing of a semiconductor substrate |
| 01/09/2001 | US6172330 Method and apparatus for forming a through hole in a ceramic green sheet |
| 01/09/2001 | US6172322 Annealing an amorphous film using microwave energy |
| 01/09/2001 | US6172318 Base for wire bond checking |
| 01/09/2001 | US6172008 Process for preparing high crystallinity oxide thin film |
| 01/09/2001 | US6171982 Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same |
| 01/09/2001 | US6171981 Electrode passivation layer of semiconductor device and method for forming the same |
| 01/09/2001 | US6171980 Polyimide coating process with dilute TMAH and DI-water backrinse |
| 01/09/2001 | US6171979 Semiconductor device and method of producing the same |
| 01/09/2001 | US6171978 Method of manufacturing capacitor dielectric |
| 01/09/2001 | US6171977 Semiconductor device applied to composite insulative film manufacturing method thereof |
| 01/09/2001 | US6171976 Method of chemical-mechanical polishing |
| 01/09/2001 | US6171975 Wet-chemical treatment method, treatment method of semiconductor substrate, and manufacturing method of semiconductor device |
| 01/09/2001 | US6171974 High selectivity oxide etch process for integrated circuit structures |
| 01/09/2001 | US6171973 Process for etching the gate in MOS technology using a SiON-based hard mask |
| 01/09/2001 | US6171971 Freestanding multilayer wiring structure |
| 01/09/2001 | US6171970 Method for forming high-density integrated circuit capacitors |
| 01/09/2001 | US6171969 Uniform dopant distribution for mesas of semiconductors |
| 01/09/2001 | US6171968 Method of forming damascene structure having borderless via design |
| 01/09/2001 | US6171967 Method for forming a self-aligned metal wire of a semiconductor device |
| 01/09/2001 | US6171966 Delineation pattern for epitaxial depositions |
| 01/09/2001 | US6171965 Treatment method of cleaved film for the manufacture of substrates |
| 01/09/2001 | US6171964 Method of forming a conductive spacer in a via |
| 01/09/2001 | US6171963 Method for forming a planar intermetal dielectric using a barrier layer |
| 01/09/2001 | US6171962 Shallow trench isolation formation without planarization mask |
| 01/09/2001 | US6171961 Fabrication method of a semiconductor device |
| 01/09/2001 | US6171960 Method of fabricating copper interconnection |
| 01/09/2001 | US6171959 Method for making a semiconductor device |
| 01/09/2001 | US6171958 Process for preparation of diffusion barrier for semiconductor |
| 01/09/2001 | US6171957 Manufacturing method of semiconductor device having high pressure reflow process |
| 01/09/2001 | US6171956 Method for improving the thermal conductivity of metal lines in integrated circuits |
| 01/09/2001 | US6171955 Semiconductor fabricating method |
| 01/09/2001 | US6171954 Method of manufacturing self-aligned contact |
| 01/09/2001 | US6171953 Processes for making electronic devices with rubidum barrier film |
| 01/09/2001 | US6171952 Methods of forming metallization layers and integrated circuits containing such |
| 01/09/2001 | US6171951 Dual damascene method comprising ion implanting to densify dielectric layer and forming a hard mask layer with a tapered opening |
| 01/09/2001 | US6171950 Method for forming a multilevel interconnection with low contact resistance in a semiconductor device |
| 01/09/2001 | US6171949 Low energy passivation of conductive material in damascene process for semiconductors |
| 01/09/2001 | US6171948 Method for filling structural gaps and intergrated circuitry |
| 01/09/2001 | US6171947 Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines |
| 01/09/2001 | US6171946 Pattern formation method for multi-layered electronic components |
| 01/09/2001 | US6171945 CVD nanoporous silica low dielectric constant films |
| 01/09/2001 | US6171944 Method for bringing up lower level metal nodes of multi-layered integrated circuits for signal acquisition |
| 01/09/2001 | US6171943 Forming a contact in an integrated circuit by chemical vapor deposition |
| 01/09/2001 | US6171942 Methods of forming electrically conductive lines in integrated circuit memories using self-aligned silicide blocking layers |
| 01/09/2001 | US6171941 Capacitor having platinum electrodes |
| 01/09/2001 | US6171940 Method for fabricating semiconductor devices having small dimension gate structures |
| 01/09/2001 | US6171939 Method for forming polysilicon gate electrode |
| 01/09/2001 | US6171938 Method for fabricating semiconductor device capable of minimizing damage of lower layer using insulating layer resided in opening |
| 01/09/2001 | US6171937 Process for producing an MOS transistor |
| 01/09/2001 | US6171936 Method of producing co-planar Si and Ge composite substrate |
| 01/09/2001 | US6171935 Process for producing an epitaxial layer with laterally varying doping |
| 01/09/2001 | US6171934 Recovery of electronic properties in process-damaged ferroelectrics by voltage-cycling |
| 01/09/2001 | US6171933 Semiconductor wafer cleaving method and apparatus |
| 01/09/2001 | US6171932 Semiconductor substrate and production method thereof |
| 01/09/2001 | US6171931 Wafer of semiconductor material for fabricating integrated devices, and process for its fabrication |
| 01/09/2001 | US6171930 Device isolation structure and device isolation method for a semiconductor power integrated circuit |
| 01/09/2001 | US6171929 Shallow trench isolator via non-critical chemical mechanical polishing |
| 01/09/2001 | US6171928 Method of fabricating shallow trench insolation |
| 01/09/2001 | US6171927 Semiconductor device structure with differential field oxide thicknesses |
| 01/09/2001 | US6171926 Methods for fabricating integrated circuit capacitor electrodes using first and second insulating layers and a buffer layer |
| 01/09/2001 | US6171925 Capacitor, and methods for forming a capacitor |
| 01/09/2001 | US6171924 Method of fabricating a dynamic random access memory capacitor |
| 01/09/2001 | US6171923 Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor |
| 01/09/2001 | US6171922 SiCr thin film resistors having improved temperature coefficients of resistance and sheet resistance |
| 01/09/2001 | US6171920 Method of forming heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction |
| 01/09/2001 | US6171919 MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation |
| 01/09/2001 | US6171918 Depleted poly mosfet structure and method |
| 01/09/2001 | US6171917 Transistor sidewall spacers composed of silicon nitride CVD deposited from a high density plasma source |
| 01/09/2001 | US6171916 Semiconductor device having buried gate electrode with silicide layer and manufacture method thereof |
| 01/09/2001 | US6171915 Method of fabricating a MOS-type transistor |
| 01/09/2001 | US6171914 Synchronized implant process to simplify NLDD/PLDD stage and N+/P+stage into one implant |
| 01/09/2001 | US6171913 Process for manufacturing a single asymmetric pocket implant |
| 01/09/2001 | US6171912 Method of manufacturing a semiconductor device comprising a field effect transistor |
| 01/09/2001 | US6171911 Method for forming dual gate oxides on integrated circuits with advanced logic devices |
| 01/09/2001 | US6171910 Method for forming a semiconductor device |
| 01/09/2001 | US6171909 Method for forming a stacked gate |
| 01/09/2001 | US6171908 Method of fabricating self-aligned split gate flash memory cell |
| 01/09/2001 | US6171907 Method for fabricating tunnel window in EEPROM cell with reduced cell pitch |
| 01/09/2001 | US6171906 Method of forming sharp beak of poly to improve erase speed in split gate flash |
| 01/09/2001 | US6171905 Semiconductor device and method of manufacturing the same |
| 01/09/2001 | US6171904 Method for forming rugged polysilicon capacitor |
| 01/09/2001 | US6171903 Method for forming a cylinder-shaped capacitor using a dielectric mask |
| 01/09/2001 | US6171902 Method of forming a DRAM cylinder shaped capacitor |
| 01/09/2001 | US6171901 Process for forming a capacitor structure |
| 01/09/2001 | US6171900 CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET |
| 01/09/2001 | US6171899 Method for fabricating a capacitor |
| 01/09/2001 | US6171898 Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K-DRAMS using a disposable-oxide processing |
| 01/09/2001 | US6171897 Method for manufacturing CMOS semiconductor device |
| 01/09/2001 | US6171896 Method of forming shallow trench isolation by HDPCVD oxide |
| 01/09/2001 | US6171895 Fabrication of buried channel devices with shallow junction depth |
| 01/09/2001 | US6171894 Method of manufacturing BICMOS integrated circuits on a conventional CMOS substrate |
| 01/09/2001 | US6171893 Method for forming self-aligned silicided MOS transistors with ESD protection improvement |
| 01/09/2001 | US6171892 Method of manufacturing a semiconductor integrated circuit device |
| 01/09/2001 | US6171891 Method of manufacture of CMOS device using additional implant regions to enhance ESD performance |