| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 02/13/2001 | US6188097 Rough electrode (high surface area) from Ti and TiN |
| 02/13/2001 | US6188096 DRAM cell capacitor having increased trench capacitance |
| 02/13/2001 | US6188095 6¼ f2 DRAM cell structure with four nodes per bitline-stud and two topological wordline levels |
| 02/13/2001 | US6188090 Semiconductor device having a heteroepitaxial substrate |
| 02/13/2001 | US6188087 Semiconductor light-emitting device |
| 02/13/2001 | US6188085 Thin film transistor and a method of manufacturing thereof |
| 02/13/2001 | US6188071 Feedback method for increasing stability of electron beams |
| 02/13/2001 | US6188050 System and method for controlling process temperatures for a semi-conductor wafer |
| 02/13/2001 | US6188044 High-performance energy transfer system and method for thermal processing applications |
| 02/13/2001 | US6188021 Package stack via bottom leaded plastic (BLP) packaging |
| 02/13/2001 | US6187874 Comprising, as a resin component, two polyimide resins different in glass transition temperature by at least 20 degrees c from each other, and an epoxy resin |
| 02/13/2001 | US6187730 Hydroxylamine-gallic compound composition and process |
| 02/13/2001 | US6187704 Obtained by sintering a homogeneous mixture of the silicon carbide powder and a non-metal-based sintering auxiliary which produces carbon upon heating. |
| 02/13/2001 | US6187694 Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer |
| 02/13/2001 | US6187693 Having a high dielectric constant suitable for use in a high density dram, and a small leakage current. |
| 02/13/2001 | US6187692 Method for forming an insulating film |
| 02/13/2001 | US6187691 Method of forming film on semiconductor substrate in film-forming apparatus |
| 02/13/2001 | US6187690 Methods of manufacturing semiconductive wafers and semiconductive material stencil masks |
| 02/13/2001 | US6187689 Manufacture of semiconductor device with fine patterns |
| 02/13/2001 | US6187688 Pattern formation method |
| 02/13/2001 | US6187687 Minimization of line width variation in photolithography |
| 02/13/2001 | US6187686 High degree of etching selectivity between the platinum layer and the mask layer can thus be achieved thereby reducing sidewall erosion and residue generation. |
| 02/13/2001 | US6187685 Method and apparatus for etching a substrate |
| 02/13/2001 | US6187684 Methods for cleaning substrate surfaces after etch operations |
| 02/13/2001 | US6187683 Method for final passivation of integrated circuit |
| 02/13/2001 | US6187682 Inert plasma gas surface cleaning process performed insitu with physical vapor deposition (PVD) of a layer of material |
| 02/13/2001 | US6187681 Method and apparatus for planarization of a substrate |
| 02/13/2001 | US6187680 Method/structure for creating aluminum wirebound pad on copper BEOL |
| 02/13/2001 | US6187679 Low temperature formation of low resistivity titanium silicide |
| 02/13/2001 | US6187677 Integrated circuitry and methods of forming integrated circuitry |
| 02/13/2001 | US6187676 Integrated circuit insulated electrode forming methods using metal silicon nitride layers, and insulated electrodes so formed |
| 02/13/2001 | US6187675 Method for fabrication of a low resistivity MOSFET gate with thick metal silicide on polysilicon |
| 02/13/2001 | US6187674 Manufacturing method capable of preventing corrosion and contamination of MOS gate |
| 02/13/2001 | US6187673 Small grain size, conformal aluminum interconnects and method for their formation |
| 02/13/2001 | US6187672 Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing |
| 02/13/2001 | US6187671 Method of forming semiconductor device having minute contact hole |
| 02/13/2001 | US6187670 Multi-stage method for forming optimized semiconductor seed layers |
| 02/13/2001 | US6187669 Method of forming a node contact of a DRAM's memory cell |
| 02/13/2001 | US6187668 Method of forming self-aligned unlanded via holes |
| 02/13/2001 | US6187667 Method of forming metal layer(s) and/or antireflective coating layer(s) on an integrated circuit |
| 02/13/2001 | US6187666 CVD plasma process to fill contact hole in damascene process |
| 02/13/2001 | US6187665 Process for deuterium passivation and hot carrier immunity |
| 02/13/2001 | US6187664 Method for forming a barrier metallization layer |
| 02/13/2001 | US6187663 Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials |
| 02/13/2001 | US6187662 Semiconductor device with low permittivity interlayer insulating film and method of manufacturing the same |
| 02/13/2001 | US6187661 Method for fabricating metal interconnect structure |
| 02/13/2001 | US6187659 Node process integration technology to improve data retention for logic based embedded dram |
| 02/13/2001 | US6187657 Dual material gate MOSFET technique |
| 02/13/2001 | US6187656 CVD-based process for manufacturing stable low-resistivity poly-metal gate electrodes |
| 02/13/2001 | US6187655 Method for performing a pre-amorphization implant (PAI) which provides reduced resist protect oxide damage and reduced junction leakage |
| 02/13/2001 | US6187654 Techniques for maintaining alignment of cut dies during substrate dicing |
| 02/13/2001 | US6187653 Method for attractive bonding of two crystalline substrates |
| 02/13/2001 | US6187651 Methods of forming trench isolation regions using preferred stress relieving layers and techniques to inhibit the occurrence of voids |
| 02/13/2001 | US6187650 Method for improving global planarization uniformity of a silicon nitride layer used in the formation of trenches by using a sandwich stop layer |
| 02/13/2001 | US6187649 Shallow trench isolation process |
| 02/13/2001 | US6187648 Method of forming a device isolation region |
| 02/13/2001 | US6187647 Method of manufacturing lateral high-Q inductor for semiconductor devices |
| 02/13/2001 | US6187646 Method of manufacturing a capacitor as part of an integrated semiconductor circuit |
| 02/13/2001 | US6187645 Method for manufacturing semiconductor device capable of preventing gate-to-drain capacitance and eliminating birds beak formation |
| 02/13/2001 | US6187644 Method of removing oxynitride by forming an offset spacer |
| 02/13/2001 | US6187643 Simplified semiconductor device manufacturing using low energy high tilt angle and high energy post-gate ion implantation (PoGI) |
| 02/13/2001 | US6187642 Method and apparatus for making mosfet's with elevated source/drain extensions |
| 02/13/2001 | US6187641 Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region |
| 02/13/2001 | US6187640 Semiconductor device manufacturing method including various oxidation steps with different concentration of chlorine to form a field oxide |
| 02/13/2001 | US6187639 Method to prevent gate oxide damage by post poly definition implantation |
| 02/13/2001 | US6187638 Method for manufacturing memory cell with increased threshold voltage accuracy |
| 02/13/2001 | US6187637 Method for increasing isolation ability using shallow trench |
| 02/13/2001 | US6187636 Flash memory device and fabrication method thereof |
| 02/13/2001 | US6187633 Novel o/n/sion/o structure, forming a silicon oxynitride layer on the silicon nitride layer. |
| 02/13/2001 | US6187632 Anneal technique for reducing amount of electronic trap in gate oxide film of transistor |
| 02/13/2001 | US6187631 Contact window is etched in an insulating layer to expose a circuit node; layer of titanium nitride is deposited over the insulating layer and into the contact window. |
| 02/13/2001 | US6187630 Method for forming hemispherical silicon grains on designated areas of silicon layer |
| 02/13/2001 | US6187629 Method of fabricating a DRAM capacitor |
| 02/13/2001 | US6187628 Semiconductor processing method of forming hemispherical grain polysilicon and a substrate having a hemispherical grain polysilicon layer |
| 02/13/2001 | US6187627 Lading plug contact pattern for DRAM application |
| 02/13/2001 | US6187626 Forming a semi-recessed capacitor structure in an inter-polysilicon dielectric |
| 02/13/2001 | US6187625 Method of fabricating crown capacitor |
| 02/13/2001 | US6187624 Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device |
| 02/13/2001 | US6187623 Method of manufacturing semiconductor device |
| 02/13/2001 | US6187622 Semiconductor memory device and method for producing the same |
| 02/13/2001 | US6187621 Semiconductor processing methods of forming capacitor constructions and semiconductor processing methods of forming DRAM constructions |
| 02/13/2001 | US6187620 Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions |
| 02/13/2001 | US6187619 Method to fabricate short-channel MOSFETs with an improvement in ESD resistance |
| 02/13/2001 | US6187618 Vertical bipolar SRAM cell, array and system, and a method for making the cell and the array |
| 02/13/2001 | US6187617 Semiconductor structure having heterogeneous silicide regions and method for forming same |
| 02/13/2001 | US6187616 Method for fabricating semiconductor device and heat treatment apparatus |
| 02/13/2001 | US6187615 Chip scale packages and methods for manufacturing the chip scale packages at wafer level |
| 02/13/2001 | US6187614 Electronic component, method for making the same, and lead frame and mold assembly for use therein |
| 02/13/2001 | US6187613 Process for underfill encapsulating flip chip driven by pressure |
| 02/13/2001 | US6187612 Molded ball grid array package mold die |
| 02/13/2001 | US6187611 Monolithic surface mount semiconductor device and method for fabricating same |
| 02/13/2001 | US6187610 Flexible thin film ball grid array containing solder mask |
| 02/13/2001 | US6187607 Manufacturing method for micromechanical component |
| 02/13/2001 | US6187606 Avoids the cracking and other problems |
| 02/13/2001 | US6187605 Method of forming a semiconductor device for a light valve |
| 02/13/2001 | US6187604 Method of making field emitters using porous silicon |
| 02/13/2001 | US6187602 CMOS integrated circuit device and its inspecting method and device |
| 02/13/2001 | US6187600 Is etched by using a mixed solution which contains ammonium hydroxide, hydrogen peroxide and water; density of the etch pits which have occurred in a surface of the silicon substrate is measured. |
| 02/13/2001 | US6187519 Process and equipment for recovering developer from photoresist development waste and reusing it |
| 02/13/2001 | US6187506 Antireflective coating for photoresist compositions |