| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 02/06/2001 | US6184623 Method for controlling plasma-generating high frequency power, and plasma generating apparatus |
| 02/06/2001 | US6184589 Constraining ring for use in electronic packaging |
| 02/06/2001 | US6184588 SRAM cell having bit line shorter than word line |
| 02/06/2001 | US6184587 Resilient contact structures, electronic interconnection component, and method of mounting resilient contact structures to electronic components |
| 02/06/2001 | US6184586 Semiconductor device including a ball grid array |
| 02/06/2001 | US6184584 Miniaturized contact in semiconductor substrate and method for forming the same |
| 02/06/2001 | US6184581 Solder bump input/output pad for a surface mount circuit device |
| 02/06/2001 | US6184579 Double-sided electronic device |
| 02/06/2001 | US6184577 Electronic component parts device |
| 02/06/2001 | US6184576 Packaging and interconnection of contact structure |
| 02/06/2001 | US6184572 Interlevel dielectric stack containing plasma deposited fluorinated amorphous carbon films for semiconductor devices |
| 02/06/2001 | US6184571 Method and apparatus for endpointing planarization of a microelectronic substrate |
| 02/06/2001 | US6184569 Semiconductor chip inspection structures |
| 02/06/2001 | US6184566 Method and structure for isolating semiconductor devices after transistor formation |
| 02/06/2001 | US6184564 Schottky diode with adjusted barrier height and process for its manufacture |
| 02/06/2001 | US6184563 Device structure for providing improved Schottky barrier rectifier |
| 02/06/2001 | US6184558 Comparator having reduced offset voltage |
| 02/06/2001 | US6184555 Field effect-controlled semiconductor component |
| 02/06/2001 | US6184554 Memory cell with self-aligned floating gate and separate select gate, and fabrication process |
| 02/06/2001 | US6184553 Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device |
| 02/06/2001 | US6184552 Non-volatile memory cell with non-trenched substrate |
| 02/06/2001 | US6184551 Capacitor with lower electrode on substrate, insulating layer including via hole so surface of lower electrode exposed, dielectric layer, and upper electrode on dielectric layer having plug of alloys of tungsten, aluminum or copper |
| 02/06/2001 | US6184550 For use as conductive barrier layers in integrated circuit memory cell structures including ferroelectric or high permittivity capacitors; the nitride-carbide material includes specified metal(s) |
| 02/06/2001 | US6184549 Trench storage dynamic random access memory cell with vertical transfer device |
| 02/06/2001 | US6184547 Field effect transistor and method of fabricating the same |
| 02/06/2001 | US6184543 Optical semiconductor device and method for fabricating the same |
| 02/06/2001 | US6184541 Thin film transistor and method of producing the same |
| 02/06/2001 | US6184536 Ion implantation process |
| 02/06/2001 | US6184532 Ion source |
| 02/06/2001 | US6184498 Apparatus for thermally processing semiconductor wafer |
| 02/06/2001 | US6184488 Low inductance large area coil for an inductively coupled plasma source |
| 02/06/2001 | US6184465 Semiconductor package |
| 02/06/2001 | US6184463 Integrated circuit package for flip chip |
| 02/06/2001 | US6184337 Heat resistance; for use in semiconductors |
| 02/06/2001 | US6184263 Blends containing photosensitive high performance aromatic ether curable polymers |
| 02/06/2001 | US6184260 Alkylating a silicone resin with a 1-alkene |
| 02/06/2001 | US6184160 Method of making an hermetically sealed implantable medical device having a vacuum-treated liquid electrolyte-filled flat electrolytic capacitor |
| 02/06/2001 | US6184159 Interlayer dielectric planarization process |
| 02/06/2001 | US6184158 Inductively coupled plasma CVD |
| 02/06/2001 | US6184157 Stress-loaded film and method for same |
| 02/06/2001 | US6184155 Method for forming a ultra-thin gate insulator layer |
| 02/06/2001 | US6184154 Method of processing the backside of a wafer within an epitaxial reactor chamber |
| 02/06/2001 | US6184153 Pretreating semiconductor material with a first fluorocarbon surfactant to protect the metal component from corrosion, exposing pretreated material to an etchant bath comprising second surfactant, salt, oxide etch, agitating |
| 02/06/2001 | US6184152 Method for fabricating stacked capacitor for a dynamic random access memory |
| 02/06/2001 | US6184151 Method for forming cornered images on a substrate and photomask formed thereby |
| 02/06/2001 | US6184150 Contacting oxide with a gas mixture including perfluorobutene and fluoromethane in presence of silicon fluorine scavenger that is spaced from oxide and nitride |
| 02/06/2001 | US6184149 Method for monitoring self-aligned contact etching |
| 02/06/2001 | US6184148 Forming on semiconductor substrate having insulation layer, layer of aluminum copper alloy; forming resist pattern on aluminum alloy layer; etching exposed layer; downstream ashing resist pattern; removing residual chlorine component |
| 02/06/2001 | US6184147 Forming silicon nitride layer on substrate, wherein silicon nitride layer serves as etching end point; forming silicon oxide layer on silicon nitride layer; performing plasma etching process in chamber to form opening in silicon oxide |
| 02/06/2001 | US6184146 Plasma producing tools, dual-source plasma etchers, dual-source plasma etching methods, and method of forming planar coil dual-source plasma etchers |
| 02/06/2001 | US6184145 Method of manufacturing semi-conductor memory device using two etching patterns |
| 02/06/2001 | US6184143 Semiconductor integrated circuit device and fabrication process thereof |
| 02/06/2001 | US6184142 Process for low k organic dielectric film etch |
| 02/06/2001 | US6184141 Method for multiple phase polishing of a conductive layer in a semidonductor wafer |
| 02/06/2001 | US6184140 Methods of making microelectronic packages utilizing coining |
| 02/06/2001 | US6184139 Oscillating orbital polisher and method |
| 02/06/2001 | US6184138 Method to create a controllable and reproducible dual copper damascene structure |
| 02/06/2001 | US6184137 Structure and method for improving low temperature copper reflow in semiconductor features |
| 02/06/2001 | US6184136 Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants |
| 02/06/2001 | US6184135 Forming insulating layer having contact opening on substrate; insitu depositing titanium silicide layer and titanium layer; etching titanium layer; rapid thermal annealing titanium silicide layer forming titanium contact layer |
| 02/06/2001 | US6184134 Dry process for cleaning residues/polymers after metal etch |
| 02/06/2001 | US6184133 Method of forming an assembly board with insulator filled through holes |
| 02/06/2001 | US6184132 Integrated cobalt silicide process for semiconductor devices |
| 02/06/2001 | US6184131 Supplying liquid material onto surface structure of substrate having recesses so as to form a layer of liquid material; pressing through exposure to high-pressure gas to fill recesses; heating to form solid layer from liquid layer |
| 02/06/2001 | US6184130 Depositing silicide layer conformally over surface of insulating layer over semiconductor substrate, where in silicide layer acts as ohmic contact and glue layer; depositing tungsten layer; removing tungsten and slicide layer |
| 02/06/2001 | US6184129 Low resistivity poly-silicon gate produced by selective metal growth |
| 02/06/2001 | US6184128 Method using a thin resist mask for dual damascene stop layer etch |
| 02/06/2001 | US6184127 Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure |
| 02/06/2001 | US6184126 Fabricating method of dual damascene |
| 02/06/2001 | US6184124 Method of making embedded wiring system |
| 02/06/2001 | US6184123 Method to prevent delamination of spin-on-glass and plasma nitride layers using ion implantation |
| 02/06/2001 | US6184122 Method for preventing crosstalk between conductive layers |
| 02/06/2001 | US6184121 Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same |
| 02/06/2001 | US6184120 Method of forming a buried plug and an interconnection |
| 02/06/2001 | US6184119 Methods for reducing semiconductor contact resistance |
| 02/06/2001 | US6184117 Method for reducing lateral silicide formation for salicide process by additional capping layer above gate |
| 02/06/2001 | US6184116 Method to fabricate the MOS gate |
| 02/06/2001 | US6184115 Method of fabricating self-aligned silicide |
| 02/06/2001 | US6184114 MOS transistor formation |
| 02/06/2001 | US6184113 Method of manufacturing a gate electrode in a semiconductor device |
| 02/06/2001 | US6184112 Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile |
| 02/06/2001 | US6184111 Pre-semiconductor process implant and post-process film separation |
| 02/06/2001 | US6184110 Method of forming nitrogen implanted ultrathin gate oxide for dual gate CMOS devices |
| 02/06/2001 | US6184109 Method of dividing a wafer and method of manufacturing a semiconductor device |
| 02/06/2001 | US6184108 Method of making trench isolation structures with oxidized silicon regions |
| 02/06/2001 | US6184107 Capacitor trench-top dielectric for self-aligned device isolation |
| 02/06/2001 | US6184106 Method for manufacturing a semiconductor device |
| 02/06/2001 | US6184105 Method for post transistor isolation |
| 02/06/2001 | US6184103 High resistance polysilicon SRAM load elements and methods of fabricating therefor |
| 02/06/2001 | US6184102 Method for manufacturing a well isolation bipolar transistor |
| 02/06/2001 | US6184101 Method of manufacturing semiconductor device requiring less manufacturing stages |
| 02/06/2001 | US6184099 Low cost deep sub-micron CMOS process |
| 02/06/2001 | US6184098 Field effect transistor device and method of manufacturing the same |
| 02/06/2001 | US6184097 Process for forming ultra-shallow source/drain extensions |
| 02/06/2001 | US6184096 Semiconductor processing method of providing dopant impurity into a semiconductor substrate |
| 02/06/2001 | US6184095 Method for fabricating mask ROM via medium current implanter |
| 02/06/2001 | US6184094 Method for producing semiconductor device |
| 02/06/2001 | US6184093 Method of implementing differential gate oxide thickness for flash EEPROM |
| 02/06/2001 | US6184092 Self-aligned contact for trench DMOS transistors |
| 02/06/2001 | US6184091 Formation of controlled trench top isolation layers for vertical transistors |