| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 01/23/2001 | US6177730 Semiconductor bare chip, method of manufacturing semiconductor bare chip and mounting structure of semiconductor bare chip |
| 01/23/2001 | US6177729 Rolling ball connector |
| 01/23/2001 | US6177728 Integrated circuit chip device having balanced thermal expansion |
| 01/23/2001 | US6177725 Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same |
| 01/23/2001 | US6177722 Leadless array package |
| 01/23/2001 | US6177719 Chip scale package of semiconductor |
| 01/23/2001 | US6177718 Resin-sealed semiconductor device |
| 01/23/2001 | US6177717 Low-noise vertical bipolar transistor and corresponding fabrication process |
| 01/23/2001 | US6177716 Low loss capacitor structure |
| 01/23/2001 | US6177715 Integrated circuit having a level of metallization of variable thickness |
| 01/23/2001 | US6177714 Semiconductor device having a fuse of the laser make-link programming type |
| 01/23/2001 | US6177707 Semiconductor device comprising a glass supporting body onto which a substrate with semiconductor elements and a metalization is attached by means of an adhesive |
| 01/23/2001 | US6177704 Semiconductor device containing a lateral MOS transistor |
| 01/23/2001 | US6177703 Method and apparatus for producing a single polysilicon flash EEPROM having a select transistor and a floating gate transistor |
| 01/23/2001 | US6177702 Semiconductor component with a split floating gate and tunnel region |
| 01/23/2001 | US6177701 Semiconductor device with resistor and fabrication method therof |
| 01/23/2001 | US6177700 Capacitor in a dynamic random access memory |
| 01/23/2001 | US6177699 DRAM cell having a verticle transistor and a capacitor formed on the sidewalls of a trench isolation |
| 01/23/2001 | US6177698 Formation of controlled trench top isolation layers for vertical transistors |
| 01/23/2001 | US6177696 Integration scheme enhancing deep trench capacitance in semiconductor integrated circuit devices |
| 01/23/2001 | US6177695 DRAM using oxide plug in bitline contacts during fabrication |
| 01/23/2001 | US6177693 Semiconductor device |
| 01/23/2001 | US6177692 Solid-state image sensor output MOSFET circuit |
| 01/23/2001 | US6177691 Cell based array having compute drive ratios of N:1 |
| 01/23/2001 | US6177688 Low defect densities |
| 01/23/2001 | US6177687 Semiconductor device having gate electrode shared between two sets of active regions and fabrication thereof |
| 01/23/2001 | US6177685 Nitride-type III-V HEMT having an InN 2DEG channel layer |
| 01/23/2001 | US6177681 Apparatus method for testing opening state for hole in semiconductor device |
| 01/23/2001 | US6177679 Ion implanter with impurity interceptor which removes undesired impurities from the ion beam |
| 01/23/2001 | US6177661 Heated stage for holding wafers during semiconductor device fabrication |
| 01/23/2001 | US6177646 Method and device for plasma treatment |
| 01/23/2001 | US6177499 Crosslinked polymethylmethacrylate (?pmma?), of the type usable in or designed for architectural uses |
| 01/23/2001 | US6177364 Integration of low-K SiOF for damascene structure |
| 01/23/2001 | US6177363 Providing an oxide layer on a semiconductor substrate, depositing nitride layer on oxide layer to introduce defects in nitride layer such that a defect density is sufficiently large to provide a low interfacial trap density |
| 01/23/2001 | US6177362 Fabrication method for gate structure having gate dielectric layers of different thickness |
| 01/23/2001 | US6177361 In-situ formation of metal oxide and ferroelectric oxide films |
| 01/23/2001 | US6177360 Positioning a layer of a dielectric precursors selected from a silsesquioxane and a photosensitive amine generator selected from carbamates, benzyl sulfonamides etc, heating to generate amine, reacting with silsesquionxane to form dielectic |
| 01/23/2001 | US6177359 Method for detaching an epitaxial layer from one substrate and transferring it to another substrate |
| 01/23/2001 | US6177358 Photo-stimulated etching of CaF2 |
| 01/23/2001 | US6177357 Laminating a resist on a polymeric film, exposing a pattern into the resist, developing resist with a aqueous solution to form an image, etching portions of polymer film not covered by crosslinked resist with a base, then stripping the resist |
| 01/23/2001 | US6177356 Semiconductor cleaning apparatus |
| 01/23/2001 | US6177355 Pad etch process capable of thick titanium nitride arc removal |
| 01/23/2001 | US6177354 Method of etching a substrate |
| 01/23/2001 | US6177353 Metallization etching techniques for reducing post-etch corrosion of metal lines |
| 01/23/2001 | US6177352 Method for producing semiconductor bodies with an MOVPE layer sequence |
| 01/23/2001 | US6177351 Method and structure for etching a thin film perovskite layer |
| 01/23/2001 | US6177350 Sputter etching the patterned dielectric surface, depositing a continuous wetting layer of titanim over the patterned dielectric surface using ion sputtering, covering the wetting layer with a layer of aluminum |
| 01/23/2001 | US6177349 Chemically treating wafer surface with a solution of ammonium fluoride, diammonium hydrogen citrate, and triammonium citrate, a surfactant and water to remove a segment of dielectric material form the surface of open dielectric field |
| 01/23/2001 | US6177348 Low temperature via fill using liquid phase transport |
| 01/23/2001 | US6177347 Silicon nitride layer within via is removed wherein copper line underlying the silicon nitride layer is exposed within the via, exposed copper line is oxidized forming opper oxide, cleaning the via and reducing oxide to form copper |
| 01/23/2001 | US6177346 Integrated circuitry and method of forming a field effect transistor |
| 01/23/2001 | US6177345 Method of silicide film formation onto a semiconductor substrate |
| 01/23/2001 | US6177344 BPSG reflow method to reduce thermal budget for next generation device including heating in a steam ambient |
| 01/23/2001 | US6177343 Process for producing semiconductor devices including an insulating layer with an impurity |
| 01/23/2001 | US6177342 Method of forming dual damascene interconnects using glue material as plug material |
| 01/23/2001 | US6177341 Method for forming interconnections in semiconductor devices |
| 01/23/2001 | US6177340 Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure |
| 01/23/2001 | US6177339 Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
| 01/23/2001 | US6177338 Two step barrier process |
| 01/23/2001 | US6177337 Method of reducing metal voids in semiconductor device interconnection |
| 01/23/2001 | US6177336 Method for fabricating a metal-oxide semiconductor device |
| 01/23/2001 | US6177335 Method of forming polycide |
| 01/23/2001 | US6177334 Manufacturing method capable of preventing corrosion of metal oxide semiconductor |
| 01/23/2001 | US6177333 Method for making a trench isolation for semiconductor devices |
| 01/23/2001 | US6177332 Method of manufacturing shallow trench isolation |
| 01/23/2001 | US6177331 Method for manufacturing semiconductor device |
| 01/23/2001 | US6177330 Method for correcting alignment, method for manufacturing a semiconductor device and a semiconductor device |
| 01/23/2001 | US6177329 Integrated circuit structures having gas pockets and method for forming integrated circuit structures having gas pockets |
| 01/23/2001 | US6177328 Methods of forming capacitors methods of forming DRAM cells, and integrated circuits incorporating structures and DRAM cell structures |
| 01/23/2001 | US6177327 Method of manufacturing capacitor for mixed-moded circuit device |
| 01/23/2001 | US6177326 Method to form bottom electrode of capacitor |
| 01/23/2001 | US6177325 Self-aligned emitter and base BJT process and structure |
| 01/23/2001 | US6177324 ESD protection device for STI deep submicron technology |
| 01/23/2001 | US6177323 Method to form MOSFET with an elevated source/drain for PMOSFET |
| 01/23/2001 | US6177322 High voltage transistor with high gated diode breakdown voltage |
| 01/23/2001 | US6177321 Semiconductor device and fabrication method thereof |
| 01/23/2001 | US6177320 Method for forming a self aligned contact in a semiconductor device |
| 01/23/2001 | US6177319 Method of manufacturing salicide layer |
| 01/23/2001 | US6177318 Integration method for sidewall split gate monos transistor |
| 01/23/2001 | US6177317 Method of making nonvolatile memory devices having reduced resistance diffusion regions |
| 01/23/2001 | US6177316 Post barrier metal contact implantation to minimize out diffusion for NAND device |
| 01/23/2001 | US6177315 Method of fabricating a high density EEPROM array |
| 01/23/2001 | US6177314 Method of manufacturing a semiconductor device comprising a field effect transistor |
| 01/23/2001 | US6177313 Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cell |
| 01/23/2001 | US6177312 Method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of such device |
| 01/23/2001 | US6177311 Method for making a floating gate memory with improved interpoly dielectric |
| 01/23/2001 | US6177310 Method for forming capacitor of memory cell |
| 01/23/2001 | US6177309 Methods of forming integrated circuit capacitors having merged annular storage electrodes therein |
| 01/23/2001 | US6177308 Method for manufacturing stacked capacitor |
| 01/23/2001 | US6177307 Process of planarizing crown capacitor for integrated circuit |
| 01/23/2001 | US6177306 Method for forming a silicide in a dynamic random access memory device |
| 01/23/2001 | US6177305 Fabrication of metal-insulator-metal capacitive structures |
| 01/23/2001 | US6177304 Self-aligned contact process using a poly-cap mask |
| 01/23/2001 | US6177303 Method of manufacturing a semiconductor device with a field effect transistor |
| 01/23/2001 | US6177302 Method of manufacturing a thin film transistor using multiple sputtering chambers |
| 01/23/2001 | US6177301 Method of fabricating thin film transistors for a liquid crystal display |
| 01/23/2001 | US6177300 Memory with storage cells having SOI drive and access transistors with tied floating body connections |
| 01/23/2001 | US6177299 Transistor having substantially isolated body and method of making the same |
| 01/23/2001 | US6177297 Method of forming metallic fuse demanding lower laser power for circuit repair |
| 01/23/2001 | US6177296 Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform |