Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
01/2001
01/17/2001EP1068214A1 Lewis base adducts of anhydrous mononuclear tris(beta-diketonate) bismuth compositions for deposition of bismuth-containing films, and method of making the same
01/17/2001EP1068047A1 Apparatus and method for film thickness measurement integrated into a wafer load/unload unit
01/17/2001EP1068020A1 Fluid nozzle system , energy emission system for photolithography and its method of manufacture
01/17/2001EP1068019A1 Energy emission system for photolithography
01/17/2001EP0800753A4 Microelectronic bonding with lead motion
01/17/2001CN1280708A Process for fabricating organic semiconductor devices using ink-jet printing technology and device and system employing same
01/17/2001CN1280687A Method and system for improving a transistor model
01/17/2001CN1280657A Gas panel
01/17/2001CN1280455A Method for producing electronic device and electronic device and resin filling method
01/17/2001CN1280392A Capacitor of somiconductor storage element
01/17/2001CN1280391A Capacitor of semiconductor storage element and its producing method
01/17/2001CN1280390A Capacitor of semiconductor storage element and its producing method
01/17/2001CN1280389A New contact shape of giga stage no-boundary contact and its producing method
01/17/2001CN1280388A Silicon complementary metal oxide semiconductor body contact on insulator formed by grating
01/17/2001CN1280387A Metal material for electronic unit, electronic unit, electronic equipment and treating method for metal material
01/17/2001CN1280386A Equipment and method for screening test of fault leakage of storage device
01/17/2001CN1280385A Method for producing surface adhered rectifying diode
01/17/2001CN1280384A Method and equipment for reducing non-uniform area influence in semiconductor device production
01/17/2001CN1280383A Method for producing semiconductor unit, method for producing solar cell and anodizing process equipment
01/17/2001CN1280343A Semiconductor processing control system and record medium for recording its processing
01/17/2001CN1280324A Equipment and method for automatically controlling semiconductor producing technology
01/17/2001CN1280323A Semiconductor factory automation system and method for processing semiconductor wafer cartridge
01/17/2001CN1280315A Method for forming photoetching offset plate figure
01/17/2001CN1280314A Method for producing semiconductor device
01/17/2001CN1280308A Film transistor array and its producing method
01/17/2001CN1280209A Compound for forming A102 film by using chemical steam deposition and method for preparing said compound
01/17/2001CN1280172A Composition for cleaning photoetching glue in integrated circuit production
01/17/2001CN1280049A Conducting real time control to chemical mechanical polishing process of measuring shaft deformation
01/16/2001US6175886 Semiconductor integrated circuit with low-power bus structure and system for composing low-power bus structure
01/16/2001US6175777 Method for transferring wafer cassettes after checking whether process equipment is in a suitable mode
01/16/2001US6175646 Apparatus for detecting defective integrated circuit dies in wafer form
01/16/2001US6175525 Non-volatile storage latch
01/16/2001US6175516 Semiconductor device
01/16/2001US6175515 Vertically integrated magnetic memory
01/16/2001US6175481 Semiconductor device having a deactivation fuse
01/16/2001US6175418 Multiple alignment mechanism in close proximity to a shared processing device
01/16/2001US6175405 Projection exposure method and method of manufacturing a projection exposure apparatus
01/16/2001US6175404 Exposure apparatus having dynamically isolated reaction frame
01/16/2001US6175263 Back bias generator having transfer transistor with well bias
01/16/2001US6175162 Semiconductor wafer having a bottom surface protective coating
01/16/2001US6175161 System and method for packaging integrated circuits
01/16/2001US6175157 Semiconductor device package for suppressing warping in semiconductor chips
01/16/2001US6175156 Semiconductor device with improved interconnection
01/16/2001US6175155 Selectively formed contact structure
01/16/2001US6175153 Semiconductor device
01/16/2001US6175152 Semiconductor device
01/16/2001US6175150 Plastic-encapsulated semiconductor device and fabrication method thereof
01/16/2001US6175147 Device isolation for semiconductor devices
01/16/2001US6175146 Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry
01/16/2001US6175144 Advanced isolation structure for high density semiconductor devices
01/16/2001US6175143 Schottky barrier
01/16/2001US6175140 Semiconductor device using a shallow trench isolation
01/16/2001US6175138 Semiconductor memory device and method of manufacturing the same
01/16/2001US6175137 Monolithic resistor having dynamically controllable impedance and method of manufacturing the same
01/16/2001US6175136 Method of forming CMOS device with improved lightly doped drain structure
01/16/2001US6175135 Trench contact structure of silicon on insulator
01/16/2001US6175134 Thin film transistors
01/16/2001US6175133 Flash memory cell and method of fabricating the same
01/16/2001US6175132 Semiconductor memory device and method of fabricating the same
01/16/2001US6175131 Semiconductor device having a capacitor and an interconnect layer
01/16/2001US6175130 DRAM having a cup-shaped storage node electrode recessed within a semiconductor substrate
01/16/2001US6175129 Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures
01/16/2001US6175128 Process for building borderless bitline, wordline and DRAM structure and resulting structure
01/16/2001US6175127 Stack capacitor having a diffusion barrier
01/16/2001US6175121 Block mask and charged particle beam exposure method and apparatus using the same
01/16/2001US6174824 Post-processing a completed semiconductor device
01/16/2001US6174823 Methods of forming a barrier layer
01/16/2001US6174822 Semiconductor device and method for fabricating the same
01/16/2001US6174821 Semiconductor processing method of depositing polysilicon
01/16/2001US6174820 Use of silicon oxynitride as a sacrificial material for microelectromechanical devices
01/16/2001US6174819 Sputter depositing titanium, aluminum alloy containing copper, and titanium nitride layers; forming photoresist mask having pattern; detecting defect; removing portion of photoresist mask by oxygen plasma; etching; removing mask
01/16/2001US6174818 Providing layer of polysilicon on substrate; depositing layer of silicon oxynitride; depositing layer of silicon oxide; oxynitride; coating with photoresist; patterning photoresist to form narrow line; etching to form hard mask; removing
01/16/2001US6174817 Two step oxide removal for memory cells
01/16/2001US6174816 Treatment for film surface to reduce photo footing
01/16/2001US6174815 Method for planarizing DRAM cells
01/16/2001US6174813 Dual damascene manufacturing process
01/16/2001US6174812 Copper damascene technology for ultra large scale integration circuits
01/16/2001US6174811 Positioning patterned substrate into high density physical vapor deposition chamber and depositing barrier layer of tantalum or tantalun nitride on substrate; depositing copper layers
01/16/2001US6174810 Providing semiconductor substrate; forming dielectric layer; patterning dielectric layer to form openings; forming copper layer; removing copper layer; exposing to plasma of hydrogen and nitrogen; forming siliconoxynitride layers
01/16/2001US6174809 Method for forming metal layer using atomic layer deposition
01/16/2001US6174808 Intermetal dielectric using HDP-CVD oxide and SACVD O3-TEOS
01/16/2001US6174807 Method of controlling gate dopant penetration and diffusion in a semiconductor device
01/16/2001US6174806 High pressure anneals of integrated circuit structures
01/16/2001US6174805 Setting temperature of evacuated reaction chamber to not less than temperature at which hydrogen chloride is produced by chlorine and hydrogen; feeding hydrogenated gas; placing substrate; evacuating; feeding titanium chloride and argon gas
01/16/2001US6174804 Dual damascene manufacturing process
01/16/2001US6174803 Integrated circuit device interconnection techniques
01/16/2001US6174802 Method for fabricating a self aligned contact which eliminates the key hole problem using a two step contact deposition
01/16/2001US6174801 E-beam direct writing to pattern step profiles of dielectric layers applied to fill poly via with poly line, contact with metal line, and metal via with metal line
01/16/2001US6174800 Via formation in a poly(arylene ether) inter metal dielectric layer
01/16/2001US6174799 Graded compound seed layers for semiconductors
01/16/2001US6174798 Forming titanium nitride(tin) barrier layer over insulation layer on integrated circuit structure; forming titanium seed layer over barrier layer; forming second tin barrier layer over titanium seed layer; forming main metal interconnect
01/16/2001US6174797 Silicon oxide dielectric material with excess silicon as diffusion barrier layer
01/16/2001US6174796 Semiconductor device manufacturing method
01/16/2001US6174795 Method for preventing tungsten contact plug loss after a backside pressure fault
01/16/2001US6174794 Method of making high performance MOSFET with polished gate and source/drain feature
01/16/2001US6174793 Method for enhancing adhesion between copper and silicon nitride
01/16/2001US6174792 Method of manufacturing a semiconductor device
01/16/2001US6174791 Method for a pre-amorphization
01/16/2001US6174790 Method of crystallizing amorphous silicon layer
01/16/2001US6174789 Method of dividing a compound semiconductor wafer into pellets by utilizing extremely narrow scribe regions