| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 02/20/2001 | US6191483 Package structure for low cost and ultra thin chip scale package |
| 02/20/2001 | US6191482 Semiconductor chip carrier having partially buried conductive pattern and semiconductor device using the same |
| 02/20/2001 | US6191476 Semiconductor device |
| 02/20/2001 | US6191471 Tape carrier package with two regions having leds that connect upon folding |
| 02/20/2001 | US6191470 Semiconductor-on-insulator memory cell with buried word and body lines |
| 02/20/2001 | US6191469 Overhanging separator for self-defining discontinuous film |
| 02/20/2001 | US6191467 Semiconductor device and method for fabricating the same |
| 02/20/2001 | US6191466 Semiconductor device containing a diode |
| 02/20/2001 | US6191463 Apparatus and method of improving an insulating film on a semiconductor device |
| 02/20/2001 | US6191462 Nitride-oxide sidewall spacer for salicide formation |
| 02/20/2001 | US6191461 Semiconductor device including output circuit improved in electrostatic damage resistance |
| 02/20/2001 | US6191460 Identical gate conductivity type static random access memory cell |
| 02/20/2001 | US6191459 Electrically programmable memory cell array, using charge carrier traps and insulation trenches |
| 02/20/2001 | US6191458 Silicon carbide integrated circuits |
| 02/20/2001 | US6191457 Integrated circuit structure having a bipolar transistor with a thick base oxide and a field effect transistor with a thin gate oxide |
| 02/20/2001 | US6191455 Semi-conductor device protected by electrostatic protection device from electrostatic discharge damage |
| 02/20/2001 | US6191454 Protective resistance element for a semiconductor device |
| 02/20/2001 | US6191452 Thin film transistor having a stopper layer |
| 02/20/2001 | US6191451 Semiconductor device with decoupling capacitance |
| 02/20/2001 | US6191450 Semiconductor device with field shield electrode |
| 02/20/2001 | US6191449 SOI based transistor having an independent substrate potential control |
| 02/20/2001 | US6191448 Memory cell with vertical transistor and buried word and body lines |
| 02/20/2001 | US6191447 Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same |
| 02/20/2001 | US6191446 Formation and control of a vertically oriented transistor channel length |
| 02/20/2001 | US6191445 Nonvolatile semiconductor memory device and method of reading a data therefrom |
| 02/20/2001 | US6191444 Mini flash process and circuit |
| 02/20/2001 | US6191443 First capacitor electrode of a conductively doped si-ge alloy; si3n4 layer over the first capacitor electrode; dielectric layer comprising ta2o5 over the si3n4 layer; and second capacitor electrode over the ta2o5 dielectric layer |
| 02/20/2001 | US6191442 DRAM memory with TFT superposed on a trench capacitor |
| 02/20/2001 | US6191441 Ferroelectric memory device and its drive method |
| 02/20/2001 | US6191440 Charge transfer device with improved charge detection sensitivity |
| 02/20/2001 | US6191429 Projection exposure apparatus and method with workpiece area detection |
| 02/20/2001 | US6191427 Ion implantation system and method suitable for low energy ion beam implantation |
| 02/20/2001 | US6191423 Correction device for correcting the spherical aberration in particle-optical apparatus |
| 02/20/2001 | US6191399 System of controlling the temperature of a processing chamber |
| 02/20/2001 | US6191397 Heating device, method for evaluating heating device and pattern forming method |
| 02/20/2001 | US6191394 Heat treating apparatus |
| 02/20/2001 | US6191392 Method of measuring electromagnetic radiation |
| 02/20/2001 | US6191390 Heating element with a diamond sealing material |
| 02/20/2001 | US6191368 Flexible, releasable strip leads |
| 02/20/2001 | US6191367 Wiring construction body with conductive lines in a resin binder |
| 02/20/2001 | US6191183 Coating surface of substrate with silica thin film forming hydgrogen silsesquioxane resin and solvent; evaporating solvent and converting hydrogen silsesquioxane resin to silica by exposing to high energy radiation |
| 02/20/2001 | US6191086 Cleaning composition and method for removing residues |
| 02/20/2001 | US6191085 Method for cleaning semiconductor devices |
| 02/20/2001 | US6191054 Method for forming film and method for fabricating semiconductor device |
| 02/20/2001 | US6191053 High efficiency photoresist coating |
| 02/20/2001 | US6191052 Providing a substrate having an exposed undoped area, forming a nitrogen containing screen oxide layer on said undoped area of said substrate, implanting impurity ions into said substrate, annealing |
| 02/20/2001 | US6191051 Wafer storing system having vessel coated with ozone-proof material and method of storing semiconductor wafer |
| 02/20/2001 | US6191050 Interlayer dielectric with a composite dielectric stack |
| 02/20/2001 | US6191049 Method for forming oxide film in semiconductor device |
| 02/20/2001 | US6191048 Process for manufacturing composite glass/Si substrates for microwave integrated circuit fabrication |
| 02/20/2001 | US6191047 Etching process using a buffer layer |
| 02/20/2001 | US6191046 Deposition of an oxide layer to facilitate photoresist rework on polygate layer |
| 02/20/2001 | US6191045 Method of treating surface of sample |
| 02/20/2001 | US6191044 Method for forming graded LDD transistor using controlled polysilicon gate profile |
| 02/20/2001 | US6191043 Flowing an etchant gas comprising helium, oxygen, and argon into inductively coupled plasma etching reactor in which a semiconductor substrate is positioned and striking the plasma, then supplying sulfur hexafluoride to gas mixture |
| 02/20/2001 | US6191042 Method of forming node contact opening |
| 02/20/2001 | US6191041 Method of fabricating semiconductor device |
| 02/20/2001 | US6191040 Wafer surface treatment methods and systems using electrocapillarity |
| 02/20/2001 | US6191039 Method of CMP of polysilicon |
| 02/20/2001 | US6191038 Apparatus and method for chemical/mechanical polishing |
| 02/20/2001 | US6191037 Methods, apparatuses and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes |
| 02/20/2001 | US6191036 Use of photoresist focus exposure matrix array as via etch monitor |
| 02/20/2001 | US6191035 Recipe design to prevent tungsten (W) coating on wafer backside for those wafers with poly Si on wafer backside |
| 02/20/2001 | US6191034 Forming minimal size spaces in integrated circuit conductive lines |
| 02/20/2001 | US6191033 Covering with a titanium layer the surfaces of a dielectric film having contact opening through to doped substrate, oxidizing titanium, annealing in a nitriding atmosphere, then forming second oxidized titanium layer and annealing again |
| 02/20/2001 | US6191032 Thin titanium film as self-regulating filter for silicon migration into aluminum metal lines |
| 02/20/2001 | US6191031 Process for producing multi-layer wiring structure |
| 02/20/2001 | US6191030 Anti-reflective coating layer for semiconductor device |
| 02/20/2001 | US6191029 Damascene process |
| 02/20/2001 | US6191028 Method of patterning dielectric |
| 02/20/2001 | US6191027 Method of forming flat wiring layer |
| 02/20/2001 | US6191026 Method for submicron gap filling on a semiconductor substrate |
| 02/20/2001 | US6191025 Method of fabricating a damascene structure for copper medullization |
| 02/20/2001 | US6191024 Apparatus and method for manufacturing a semiconductor package |
| 02/20/2001 | US6191023 Method of improving copper pad adhesion |
| 02/20/2001 | US6191022 Fine pitch solder sphere placement |
| 02/20/2001 | US6191021 Method of forming a low-resistance contact on compound semiconductor |
| 02/20/2001 | US6191019 Method for forming a polysilicon layer in a polycide process flow |
| 02/20/2001 | US6191018 Method for selective resistivity adjustment of polycide lines for enhanced design flexibility and improved space utilization in sub-micron integrated circuits |
| 02/20/2001 | US6191017 Method of forming a multi-layered dual-polysilicon structure |
| 02/20/2001 | US6191016 Method of patterning a layer for a gate electrode of a MOS transistor |
| 02/20/2001 | US6191015 Method for producing a Schottky diode assembly formed on a semiconductor substrate |
| 02/20/2001 | US6191014 Metalorganic vapor phase growth of p-type semiconductor epitaxial layer doped with carbon using carbon trichloride bromide |
| 02/20/2001 | US6191012 Method for forming a shallow junction in a semiconductor device using antimony dimer |
| 02/20/2001 | US6191011 Selective hemispherical grain silicon deposition |
| 02/20/2001 | US6191010 Process for preparing an ideal oxygen precipitating silicon wafer |
| 02/20/2001 | US6191008 Method of forming SOI substrate which includes forming trenches during etching of top semiconductor layer |
| 02/20/2001 | US6191007 Method for manufacturing a semiconductor substrate |
| 02/20/2001 | US6191006 Method of bonding a III-V group compound semiconductor layer on a silicon substrate |
| 02/20/2001 | US6191005 Process for producing semiconductor device |
| 02/20/2001 | US6191004 Method of fabricating shallow trench isolation using high density plasma CVD |
| 02/20/2001 | US6191003 Method for planarizing a polycrystalline silicon layer deposited on a trench |
| 02/20/2001 | US6191002 Method of forming trench isolation structure |
| 02/20/2001 | US6191001 Shallow trench isolation method |
| 02/20/2001 | US6191000 Shallow trench isolation method used in a semiconductor wafer |
| 02/20/2001 | US6190999 Method for fabricating a shallow trench isolation structure |
| 02/20/2001 | US6190998 Method for achieving a thin film of solid material and applications of this method |
| 02/20/2001 | US6190996 Method of making an insulator for electrical structures |
| 02/20/2001 | US6190995 Method of fabricating shallow trench isolation structure |
| 02/20/2001 | US6190994 Forming a sacrificial polysilicon protective coating on a dielectric layer, then forming tungsten nucleation layer by reduction of tungsten hexafluoride with the sacrificial polysilicon layer, forming final tungsten layer |