Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2001
03/13/2001US6200902 Simultaneously etching polysilicon layer in groove of memory cell section and polysilicon layer in peripheral circuit section using chlorine/hydrogn bromide gas until polysilicon in peripheral section is exposed, further etching
03/13/2001US6200901 Polishing polymer surfaces on non-porous CMP pads
03/13/2001US6200900 Method for formation of an air gap in an integrated circuit architecture
03/13/2001US6200899 Brush scrubbing polished surface of the wafer with aalkaline colloidal silica slurry; brush scrubbing wafer with water
03/13/2001US6200898 Removing insulator layers only from regions located between individual dynamic random access memory crown shaped storage node structures, polysilicon layer used for upper plate structure fills spaces between crown nodes
03/13/2001US6200897 Method for manufacturing even dielectric layer
03/13/2001US6200896 Employing an acidic liquid and an abrasive surface to polish a semiconductor topography
03/13/2001US6200895 Method of forming an electrical connection
03/13/2001US6200894 Method for enhancing aluminum interconnect properties
03/13/2001US6200893 Radical-assisted sequential CVD
03/13/2001US6200892 Method for forming an integrated circuit interconnect using a dual poly process
03/13/2001US6200891 Removal of dielectric oxides
03/13/2001US6200890 Method of fabricating copper damascene
03/13/2001US6200888 Method of producing semiconductor device comprising insulation layer having improved resistance and semiconductor device produced thereby
03/13/2001US6200887 Method to form a smooth gate polysilicon sidewall in the fabrication of integrated circuits
03/13/2001US6200886 Forming silicon dioxide (sio2) layer on the substrate and polysilicon gate with overlying antireflection layer; sio2 layer is removed with enough remaining to cover sidewalls of gate and substrate before removal of antireflection layer
03/13/2001US6200885 By providing a substrate such as indium phosphide, gallium arsenide, or indium gallium aresnide phosphide; treating with sulfuric acid, and coating an aluminum layer to form a schottky barrier layer and forming metal on barrier layer
03/13/2001US6200884 Method for shaping photoresist mask to improve high aspect ratio ion implantation
03/13/2001US6200883 Ion implantation method
03/13/2001US6200881 Method of forming a shallow trench isolation
03/13/2001US6200880 Method for forming shallow trench isolation
03/13/2001US6200879 Using epitaxially grown wells for reducing junction capacitances
03/13/2001US6200878 SOI substrate processing method
03/13/2001US6200877 Method of forming a charge storage electrode having a selective hemispherical grains silicon film in a semiconductor device
03/13/2001US6200876 Method of producing a semiconductor device
03/13/2001US6200875 Chemical mechanical polishing of polysilicon plug using a silicon nitride stop layer
03/13/2001US6200874 Methods for use in forming a capacitor
03/13/2001US6200873 Production method for a trench capacitor with an insulation collar
03/13/2001US6200872 Semiconductor substrate processing method
03/13/2001US6200871 High performance self-aligned silicide process for sub-half-micron semiconductor technologies
03/13/2001US6200870 Method for forming gate
03/13/2001US6200869 Method of fabricating an integrated circuit with ultra-shallow source/drain extensions
03/13/2001US6200868 Insulated gate type semiconductor device and process for producing the device
03/13/2001US6200867 Method for forming raised source and drain
03/13/2001US6200866 Use of silicon germanium and other alloys as the replacement gate for the fabrication of MOSFET
03/13/2001US6200865 Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate
03/13/2001US6200864 Method of asymmetrically doping a region beneath a gate
03/13/2001US6200863 Process for fabricating a semiconductor device having assymetric source-drain extension regions
03/13/2001US6200862 Mask for asymmetrical transistor formation with paired transistors
03/13/2001US6200861 Method of fabricating high density multiple states mask ROM cells
03/13/2001US6200860 Process for preventing the reverse tunneling during programming in split gate flash
03/13/2001US6200859 Method of fabricating a split-gate flash memory
03/13/2001US6200858 Floating gate sidewall structure for the suppression of bird's beak
03/13/2001US6200857 Method of manufacturing a semiconductor device without arc loss in peripheral circuit region
03/13/2001US6200856 Method of fabricating self-aligned stacked gate flash memory cell
03/13/2001US6200855 Semiconductor memory device, and method for fabricating thereof
03/13/2001US6200854 Method of manufacturing dynamic random access memory
03/13/2001US6200853 Method of manufacturing semiconductor device having capacitor contact holes
03/13/2001US6200852 Multiple thin silicon nitride layers are formed on respective film surface to obtain pinhole defects unmatched dielectric layer
03/13/2001US6200851 Memory cell that includes a vertical transistor and a trench capacitor
03/13/2001US6200850 Method for forming a stacked capacitor
03/13/2001US6200849 Methods of fabricating conductive contacts for integrated circuit memory devices using first and second dielectric layers and first and second conductive layers
03/13/2001US6200848 Method of fabricating self-aligned contact in embedded DRAM
03/13/2001US6200847 Method of manufacturing capacitor of semiconductor device
03/13/2001US6200846 Semiconductor device with capacitor formed on substrate and its manufacture method
03/13/2001US6200845 Method of forming a storage capacitor
03/13/2001US6200844 Method of manufacturing dielectric film of capacitor in dynamic random access memory
03/13/2001US6200843 High-voltage, high performance FETs
03/13/2001US6200842 Method of forming complementary type conductive regions on a substrate
03/13/2001US6200841 MOS transistor that inhibits punchthrough and method for fabricating the same
03/13/2001US6200840 Method for producing PMOS devices
03/13/2001US6200839 Methods of forming thin film transistors
03/13/2001US6200838 Compound semiconductor device and method of manufacturing the same
03/13/2001US6200837 Method of manufacturing thin film transistor
03/13/2001US6200836 Using oxide junction to cut off sub-threshold leakage in CMOS devices
03/13/2001US6200835 Methods of forming conductive polysilicon lines and bottom gated thin film transistors, and conductive polysilicon lines and thin film transistors
03/13/2001US6200834 Process for fabricating two different gate dielectric thicknesses using a polysilicon mask and chemical mechanical polishing (CMP) planarization
03/13/2001US6200833 Method of attaching a leadframe to singulated semiconductor dice
03/13/2001US6200832 Apparatus for applying viscous materials to a lead frame
03/13/2001US6200830 Fabrication process of a semiconductor device
03/13/2001US6200829 Microelectronic assembly with connection to a buried electrical element, and method for forming same
03/13/2001US6200828 Integrated circuit package architecture with a variable dispensed compound and method of manufacturing the same
03/13/2001US6200825 Method of manufacturing silicon based thin film photoelectric conversion device
03/13/2001US6200824 Semiconductor device and tape carrier, and method of manufacturing the same, circuit board, electronic instrument, and tape carrier manufacturing device
03/13/2001US6200823 Method for isolation of optical defect images
03/13/2001US6200822 Method for detecting the transition between different materials in semiconductor structures
03/13/2001US6200821 Method for fabricating ferroelectric random access memory device
03/13/2001US6200735 Method for forming contact hole by dry etching
03/13/2001US6200734 Method for fabricating semiconductor devices
03/13/2001US6200728 A resin blends comprising a first photoacid generator onium compound and a second photoacid generator onium compound, to produce photoacids that differ in acid strength and/or size; useful as deep u.v. photoresists, forming a relief image
03/13/2001US6200726 Selecting a desired space width, selecting at least one photoacid generator (pag), which will generate two photoacids upon exposure to actinic energy to produce a desired space width in hybrid photoresist, forming hybrid photoresist
03/13/2001US6200710 Methods for producing segmented reticles
03/13/2001US6200694 Molybdenum (mo) and tungsten (w) at a ratio in specific range having low resistivity and high workability.
03/13/2001US6200653 Method of forming an intermetal dielectric layer
03/13/2001US6200634 Thermal processing system with supplemental resistive heater and shielded optical pyrometry
03/13/2001US6200633 Coating apparatus and coating method
03/13/2001US6200629 Multilayer; dielectric, electromigration layer, metallic pattern
03/13/2001US6200433 Depositing a barrier layer in a plasma chamber having an inductive coil and a target comprising the material to be sputtered, one or more plasma gases having high molar masses relative to target material such as xenon or krypton
03/13/2001US6200415 Load controlled rapid assembly clamp ring
03/13/2001US6200414 Circulation system for supplying chemical for manufacturing semiconductor devices and circulating method thereof
03/13/2001US6200412 Chemical vapor deposition system including dedicated cleaning gas injection
03/13/2001US6200408 Method for cementing a component to a surface
03/13/2001US6200405 Method of manufacturing laminated ceramic electronic parts
03/13/2001US6200388 Substrate support for a thermal processing chamber
03/13/2001US6200387 Method and system for processing substrates using nebulized chemicals created by heated chemical gases
03/13/2001US6200382 Method of manufacturing a semiconductor laser device and a crystal growth apparatus for use in a semiconductor laser device
03/13/2001US6200201 Cleaning/buffer apparatus for use in a wafer processing device
03/13/2001US6200121 Process for concurrently molding semiconductor chips without void and wire weep and molding die used therein
03/13/2001US6200100 Method and system for preventing incontinent liquid drip
03/13/2001US6200071 Transfer apparatus and transfer method for particulate material