Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2001
03/13/2001US6200023 Method for determining the temperature in a thermal processing chamber
03/13/2001US6199991 Mirror projection system for a scanning lithographic projection apparatus, and lithographic apparatus comprising such a system
03/13/2001US6199927 Robot blade for handling of semiconductor substrates
03/13/2001US6199751 Polymer with transient liquid phase bondable particles
03/13/2001US6199743 Apparatuses for forming wire bonds from circuitry on a substrate to a semiconductor chip, and methods of forming semiconductor chip assemblies
03/13/2001US6199604 Clean box, clean transfer method and apparatus therefor
03/13/2001US6199568 Treating tank, and substrate treating apparatus having the treating tank
03/13/2001US6199567 Method and apparatus for manufacturing semiconductor device
03/13/2001US6199564 Substrate processing method and apparatus
03/13/2001US6199563 Where wafers are processed while being entirely dipped into the waffer processing bath and rotated by wafer rotating rods
03/13/2001US6199561 Method for ashing
03/13/2001US6199533 Pilot valve controlled three-way fuel injection control valve assembly
03/13/2001US6199505 Plasma processing apparatus
03/13/2001US6199298 Vapor assisted rotary drying method and apparatus
03/13/2001US6199291 Alignment fixture
03/13/2001US6199273 Method of forming connector structure for a ball-grid array
03/13/2001US6199260 Method of fixing a plurality of lower members each having reference bore for installing upper member, and fixing jigs
03/13/2001CA2192630C Fabrication process and fabrication apparatus of soi substrate
03/11/2001CA2316459A1 Ccd wafers with titanium refractory metal
03/08/2001WO2001017041A1 Method for forming a patterned semiconductor film
03/08/2001WO2001017037A1 Chemically inert megasonic transducer system
03/08/2001WO2001017031A1 Easy shrinkable novel non-volatile semiconductor memory cell utilizing split dielectric floating gate and method for making same
03/08/2001WO2001017030A1 Non-volatile memory structure for twin-bit storage and methods of making same
03/08/2001WO2001017026A1 Post-fuse blow corrosion prevention structure for copper fuses
03/08/2001WO2001017024A1 Fabrication method for pasted soi wafer and pasted soi wafer
03/08/2001WO2001017023A1 Nonvolatile memory having high gate coupling capacitance
03/08/2001WO2001017022A1 Semiconductor device with buried bitlines
03/08/2001WO2001017021A1 Encapsulated tungsten gate mos transistor and memory cell and method of making same
03/08/2001WO2001017019A2 Memory with a trench capacitor and a selection transistor and method for producing the same
03/08/2001WO2001017018A1 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate
03/08/2001WO2001017017A1 Nonvolatile ferroelectric memory and method of manufacture thereof
03/08/2001WO2001017016A2 Capacitor-over-bit line memory circuitry
03/08/2001WO2001017015A1 Method for producing a dram cell arrangement
03/08/2001WO2001017014A1 Storage cell array and a method for the manufacture thereof
03/08/2001WO2001017013A2 A method and an apparatus for forming an under bump metallization structure
03/08/2001WO2001017012A1 Device and method for encapsulating electronic components mounted on a carrier
03/08/2001WO2001017010A1 Disposable spacers for mosfet gate structure
03/08/2001WO2001017009A1 Method to fabricate a mosfet
03/08/2001WO2001017008A1 Hf-fet and method for producing the same
03/08/2001WO2001017007A1 Method of etching and method of plasma treatment
03/08/2001WO2001017006A1 Polishing compound for chemimechanical polishing and polishing method
03/08/2001WO2001017005A1 Method and apparatus for handling arranged part
03/08/2001WO2001017004A2 Method of forming a conductive silicide layer on a silicon comprising substrate and method of forming a conductive silicide contact
03/08/2001WO2001017003A1 Method of heat treatment
03/08/2001WO2001017002A1 Layer structure for bipolar transistors and method for the production thereof
03/08/2001WO2001017001A1 Method and apparatus for laser ablation of a target material
03/08/2001WO2001017000A1 Handling device for preparing a wafer stack
03/08/2001WO2001016998A2 Ultra high resolution lithographic imaging and printing and defect reduction by exposure near the critical condition
03/08/2001WO2001016960A1 1 transistor cell for eeprom application
03/08/2001WO2001016875A1 Chip card module and chip card encompassing said module as well as a method for producing the chip card module
03/08/2001WO2001016663A1 Load device
03/08/2001WO2001016659A1 Semiconductor manufacturing apparatus and method for controlling the operating condition parameter
03/08/2001WO2001016559A1 Method of and device for determining the warpage of a wafer
03/08/2001WO2001016556A1 Interferometers utilizing polarization preserving optical systems
03/08/2001WO2001016408A1 Epitaxial silicon wafer
03/08/2001WO2001016403A1 Galvanizing solution for the galvanic deposition of copper
03/08/2001WO2001016396A1 Film deposition apparatus and method
03/08/2001WO2001016395A1 Titanium containing dielectric films and methods of forming same
03/08/2001WO2001015867A1 Unsupported polishing belt for chemical mechanical polishing
03/08/2001WO2001015865A1 Apparatus and method for conditioning and monitoring media used for chemical-mechanical planarization
03/08/2001WO2001015863A1 Windowless belt and method for in-situ wafer monitoring
03/08/2001WO2001015860A1 Method and device for polishing semiconductor wafer
03/08/2001WO2001015855A1 Method and apparatus for mechanical and chemical-mechanical planarization of microelectronic substrates with metal compound abrasives
03/08/2001WO2001015819A1 Three-dimensional electrical interconnects
03/08/2001WO2001015818A1 Method and apparatus for controlling air over a spinning microelectronic substrate
03/08/2001WO2000074130A9 Discrete schottky diode device with reduced leakage current
03/08/2001WO2000068979A3 An apparatus for sensing temperature on a substrate in an integrated circuit fabrication tool
03/08/2001WO2000062331A3 Semiconductor heterostructures with crystalline silicon carbide alloyed with germanium
03/08/2001WO2000061324A3 Rocking apparatus and method for slicing a work piece utilizing a diamond impregnated wire
03/08/2001WO2000052752A3 A process for underfilling flip-chip integrated circuit package with an underfill material that is heated to a partial gel state
03/08/2001WO2000033089A3 Lithographic contact elements
03/08/2001DE19941530A1 Manufacturing electronic component with nitride layer using plasma CVD process supplies gas flow at angle to substrate surface, with deposition at specified lower temperatures
03/08/2001DE19941401C1 Verfahren zur Herstellung einer DRAM-Zellenanordnung A method of manufacturing a DRAM cell arrangement
03/08/2001DE19940278A1 Schichtstruktur für bipolare Transistoren und Verfahren zu deren Herstellung Layer structure for bipolar transistors and methods for their preparation
03/08/2001DE19939258A1 Werkzeug und Verfahren zum abrasiven Bearbeiten einer im wesentlichen ebenen Fläche A method for abrasive machining tool and a substantially flat surface
03/08/2001DE19937501A1 Higher-capacity micro-electronic DRAM condenser exhibiting merely conventional overall size, is made as trench with waviness along its vertical extent
03/08/2001DE19936905A1 Epitaxial growth of crystal, e.g. hexagonal gallium nitride, on substrate with common type of atom uses lighter substrate with rough or porous surface and thermal decomposition to release common atoms during growth
03/08/2001DE19737839C2 Transportsystem Transport system
03/08/2001DE10040392A1 Mask layout data density investigation arrangement for semiconductor device has data density computing device, temporary fault area detection device and fault area detection device
03/08/2001DE10039646A1 Metal cover placed over and enclosing e.g. piezoelectric resonator on circuit substrate, includes insulating layer on and around edges bordering its open end
03/08/2001DE10036356A1 Magnetic thin film component with diode switched by controlling spin of injected electrons
03/08/2001DE10034840A1 Flux transfer apparatus for wafer, has drive unit which is controlled to rotate transfer pin within horizontal surface during flux transfer
03/08/2001DE10033984A1 Hybridlaminat und Verfahren zur Herstellung desselben Hybrid laminate and method of manufacturing the same
03/08/2001DE10031624A1 Manufacture of FET transistor with elevated source and drain regions and minimal channel length, overlaps regions of differing dopant levels at each end of gate
03/08/2001DE10024362A1 Semiconductor device operating on basis of constant current provided by constant current circuit damps noise generated in internal circuits with buffer circuits
03/08/2001DE10023379A1 Thin film probe manufacturing method for testing integrated circuit, involves removing substrate from electrical conducting material after connecting track to electrical conducting material
03/08/2001DE10020150A1 Semiconductor SRAM with reduced storage cell area and improved data retention interval has negative resistance section with tunnel insulating layer formed on active p-type region
03/08/2001CA2384004A1 Method to fabricate a mosfet
03/07/2001EP1081990A2 A method for forming a solder ball
03/07/2001EP1081818A2 Semiconductor laser devices
03/07/2001EP1081768A2 Insulated gate field-effect transistor and method of making the same
03/07/2001EP1081763A2 Method to trap air for improving the quality factor (Q) of RF inductors in CMOS technology
03/07/2001EP1081758A1 Pressure-sensitive adhesive sheets for dicing
03/07/2001EP1081757A1 Multichip module packaging process for known good die burn-in
03/07/2001EP1081756A2 A method for producing silicon nitride series film
03/07/2001EP1081755A2 Method for improving a quality of dielectric layer and semiconductor device
03/07/2001EP1081754A2 Cleaning contact area with successive fluoride and hydrogen plasmas
03/07/2001EP1081753A2 Process to improve filling of contact holes by electroplating
03/07/2001EP1081752A1 Method to form copper interconnects by adding an aluminium layer to the diffusion barrier
03/07/2001EP1081751A2 Methods of pre-cleaning dielectric layers of substrates